Functional Pin Definitions
The following describes the function of all of the DP8224
input/output pins. Some of these descriptions reference in-
ternal circuits.
For manual system reset, a momentary contact switch that
provides a low (ground) when closed is also connected to
the RESIN input.
Ready In (RDYIN): An asynchronous READY signal that is
re-clocked by a D-type flip-flop of the DP8224 to provide the
synchronous READY output discussed below.
INPUT SIGNALS
Crystal Connections (XTAL 1 and XTAL 2): Two inputs
that connect an external crystal to the oscillator circuit of
the DP8224. Normally, a fundamental mode crystal is used
to determine the basic operating frequency of the oscillator.
However, overtone mode crystals may also be used. The
crystal frequency is 9 times the desired microprocessor
a
a
5 Volts: V
CC
supply.
supply.
12 Volts: V
DD
Ground: 0 volt reference.
OUTPUT SIGNALS
c
speed (that is, crystal frequency equals 1/t
CY
9). When
Oscillator (OSC): A buffered oscillator signal that can be
used for external timing purposes.
the crystal frequency is above 10 MHz, a selected capacitor
(3 to 10 pF) may have to be connected in series with the
crystal to produce the exact desired frequency. Figure A.
w
and w Clocks: Two non-TTL compatible clock phases
2
1
that provide nonoverlapping timing references for internal
storage elements and logic circuits of the 8080A microproc-
essor. The two clock phases are produced by an internal
clock generator that consists of a divide-by-nine counter
and the associated decode gating logic. Figure B.
Tank: Allows the use of overtone mode crystals with the
oscillator circuit. When an overtone mode crystal is used,
the tank input connects to a parallel LC network that is ac
coupled to ground. The formula for determining the reso-
nant frequency of this LC network is as follows:
w
(TTL) Clock: A TTL w clock phase that can be used for
2
external timing purposes.
1
2
e
F
2q LC
0
Status Strobe (STSTB): Activated (low) at the start of each
new machine cycle. The STSTB signal is generated by gat-
Synchronizing (SYNC) Signal: When high, indicates the
beginning of a new machine cycle. The 8080A microproces-
sor outputs a status word (which describes the current ma-
chine cycle) onto its data bus during the first state (SYNC
interval) of each machine cycle.
ing a high-level SYNC input with the w timing signal from
1A
the internal clock generator of the DP8224. The STSTB sig-
nal is used to clock status information into the status latch
of the DP8228 system controller and bus driver.
Reset In (RESIN): Provides an automatic system reset and
start-up upon application of power as follows. The RESIN
input, which is obtained from the junction of an external RC
Reset: When the RESET signal is activated, the content of
the program counter of the 8080A is cleared. After
RESET, the program will start at location 0 in memory.
network that is connected between V and ground, is rout-
CC
Ready: The READY signal indicates to the 8080A that valid
memory or input data is available. This signal is used to
synchronize the 8080A with slower memory or input/output
devices.
ed to an internal Schmitt Trigger circuit. This circuit converts
the slow transition of the power supply rise into a sharp,
clean edge when its input reaches a predetermined value.
When this occurs, an internal D-type flip-flop is synchro-
nously reset, thereby providing the RESET output signal dis-
cussed below.
Logic and Connection Diagrams
Dual-In-Line Package
TL/F/8752–5
Top View
Order Number DP8224J or DP8224N
See NS Package Number
J16A or N16A
TL/F/8752–4
5
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