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DM9316W PDF预览

DM9316W

更新时间: 2024-10-01 22:40:35
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
10页 167K
描述
Synchronous 4-Bit Counters

DM9316W 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.54
Is Samacsys:N其他特性:TCO OUTPUT
计数方向:UP系列:93
JESD-30 代码:R-GDFP-F16JESD-609代码:e0
长度:9.6645 mm负载电容(CL):15 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:25000000 Hz最大I(ol):0.016 A
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL16,.3封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):101 mA
传播延迟(tpd):25 ns认证状态:Not Qualified
座面最大高度:2.032 mm子类别:Counters
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.604 mm最小 fmax:35 MHz
Base Number Matches:1

DM9316W 数据手册

 浏览型号DM9316W的Datasheet PDF文件第2页浏览型号DM9316W的Datasheet PDF文件第3页浏览型号DM9316W的Datasheet PDF文件第4页浏览型号DM9316W的Datasheet PDF文件第5页浏览型号DM9316W的Datasheet PDF文件第6页浏览型号DM9316W的Datasheet PDF文件第7页 
June 1989  
9316/DM9316 Synchronous 4-Bit Counters  
General Description  
These synchronous, presettable counters feature an inter-  
nal carry look-ahead for application in high-speed counting  
designs. The 9316 is a 4-bit binary counter. The carry output  
is decoded by means of a NOR gate, thus preventing spikes  
during the normal counting mode of operation. Synchronous  
operation is provided by having all flip-flops clocked simulta-  
neously so that the outputs change coincident with each  
other when so instructed by the count-enables inputs and  
internal gating. This mode of operating eliminates the output  
counting spikes which are normally associated with asyn-  
chronous (ripple clock) counters. A buffered clock input trig-  
gers the four flip-flops on the rising (positive-going) edge of  
the clock input waveform.  
The carry look-ahead circuitry provides for cascading coun-  
ters for n-bit synchronous applications without additional  
gating. Instrumental in accomplishing this function are two  
count-enable inputs and a ripple carry output. Both count-  
enable inputs (P and T) must be high to count, and input T is  
fed-forward to enable the ripple carry output. The ripple car-  
ry output thus enabled will produce a high-level output pulse  
with a duration approximately equal to the high-level portion  
of the Q output. This high-level overflow ripple carry pulse  
A
can be used to enable successive cascaded stages. High-  
to-low level transitions at the enable P or T inputs may occur  
regardless of the logic level in the clock.  
Features  
Y
These counters are fully programmable; that is, the outputs  
may be preset to either level. As presetting is synchronous,  
setting up a low level at the load input disables the counter  
and causes the outputs to agree with the setup data after  
the next clock pulse regardless of the levels of the enable  
input. Low-to-high transitions at the load input are perfectly  
acceptable regardless of the logic levels on the clock or  
enable inputs. The clear function is asynchronous and a low  
level at the clear input sets of the flip-flop outputs low re-  
gardless of the levels of clock, load, or enable inputs.  
Internal look-ahead for fast counting  
Y
Carry output for n-bit cascading  
Y
Synchronous counting  
Y
Load control line  
Y
Diode-clamped inputs  
Y
Typical clock frequency 35 MHz  
Y
Pin-for-pin replacements popular 54/74 counters  
5416A/7416A (binary)  
Y
Alternate Military/Aerospace device (9316) is available.  
Contact a National Semiconductor Sales Office/Distrib-  
utor for specifications.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6606–1  
Order Number 9316DMQB, 9316FMQB, DM9316J  
DM9316W or DM9316N  
See NS Package Number J16A, N16E or W16A  
C
1995 National Semiconductor Corporation  
TL/F/6606  
RRD-B30M105/Printed in U. S. A.  

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