Datasheet > DM9102DEP

DM9102DEP

更新时间： 2024-01-10 15:01:07

品牌	Logo	应用领域
联杰 - DAVICOM		控制器以太网
页数	文件大小	规格书
70页	563K
描述
Single Chip Fast Ethernet NIC Controller

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技术参数
数据手册

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DM9102DEP 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.62
Is Samacsys：	N	Base Number Matches：	1

DM9102DEP 数据手册

5. Pin Description

I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power,

# = asserted Low

5.1 PCI Bus Interface Signals

Pin No.

128LQFP

113

Pin Name

I/O

Description

INT#

O/D Interrupt Request

This signal will be asserted low when an interrupted condition

as defined in CR5 is set, and the corresponding mask bit in

CR7 is et.

114

115

117

118

119

RST#

PCICLK

GNT#

System Reset

When this signal is low, the DM9102D performs the internal

system reset to its initial state.

PCI system clock

PCI bus clock that provides timing for DM9102D related to

PCI bus transactions.

Bus Grant

This signal is asserted low to indicate that DM9102D has

been granted ownership of the bus by the central arbiter.

Bus Request

The DM9102D will assert this signal low to request the

ownership of the bus.

REQ#

PME#

O/D Power Management Event.

The DM9102D drives it low to indicates that a power

management event has occurred.

Initialization Device Select

This signal is asserted high during the Configuration Space

read/write access.

Cycle Frame

This signal is driven low by the DM9102D master mode to

indicate the beginning and duration of a bus transaction.

Initiator Ready

IDSEL

FRAME#

IRDY#

I/O

This signal is driven low when the master is ready to

complete the current data phase of the transaction. A data

phase is completed on any clock when both IRDY# and

TRDY# are sampled asserted.

TRDY#

I/O

Target Ready

This signal is driven low when the target is ready to complete

the current data phase of the transaction. During a read, it

indicates that valid data is asserted. During a write, it

indicates that the target is prepared to accept data.

Device Select

DEVSEL#

The DM9102D asserts the signal low when it recognizes its

target address after FRAME# is asserted. As a bus master,

the DM9102D will sample this signal which insures its

destination address of the data transfer is recognized by a

target.

STOP#

I/O

Stop

This signal is asserted low by the target device to request the

Final

Version: DM9102D-DS-F01

May 10, 2006

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