DM86LS62J

更新时间： 2024-09-23 13:02:23

品牌	Logo	应用领域
美国国家半导体 - NSC		移位寄存器
页数	文件大小	规格书
8页	151K
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DM86LS62J 数据手册

August 1991

DM74LS962 (DM86LS62)

Dual Rank 8-Bit TRI-STATE Shift Register

General Description

Features

Registers are edge-triggered by the positive transition

of the clock

These circuits are TRI-STATE, edge-triggered, 8-bit I/O reg-

isters in parallel with 8-bit serial shift registers which are

capable of operating in any of the following modes: parallel

load from I/O pins to register ‘‘A’’, parallel transfer down

from register ‘‘A’’ to serial shift register ‘‘B’’, parallel transfer

up from shift register ‘‘B’’ to register ‘‘A’’, serial shift of regis-

ter ‘‘B’’, or exchange data between register ‘‘A’’ and shift

positive transition of the clock, the control lines which deter-

mine the mode or operation are completely independent of

the logic level applied to the clock. Designed for bus-orient-

ed systems, these circuits have their TRI-STATE inputs and

outputs on the same pins.

All inputs are PNP transistors

Input disable dominates over output disable

Output high impedance state does not impede any oth-

er mode of operation

8-bit I/O pins are TRI-STATE buffers

Typical shift frequency is 36 MHz

Typical power dissipation is 305 mW

All control inputs are active when in an ‘‘L’’ logic state

Devices can be cascaded into N-bit word

Connection Diagram

Dual-In-Line Package

Pin Description

DIS ÐOutput disable

I ÐSerial input

DIS ÐInput disable

DIS ÐTransfer up disable

DIS ÐTransfer down disable

DIS ÐShift disable

O ÐSerial output

CLKÐClock

GNDÐGround

I/O 1 . . . I/O 8Ð8-bit I/O pins

V ÐSupply Voltage

TL/F/6438–1

Top View

Order Number DM74LS962N or DM86LS62N

See NS Package Number N18A

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation

TL/F/6438

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7 8

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