Datasheet > DM74LS12MX

DM74LS12MX

更新时间： 2024-09-22 08:56:27

品牌	Logo	应用领域
美国国家半导体 - NSC		输入元件光电二极管
页数	文件大小	规格书
4页	106K
描述
LS SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14, PLASTIC, SOP-14

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数据手册

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DM74LS12MX 数据手册

June 1989

DM54LS12/DM74LS12 Triple 3-Input NAND Gates

with Open-Collector Outputs

General Description

Pull-Up Resistor Equations

This device contains three independent gates each of which

performs the logic NAND function. The open-collector out-

puts require external pull-up resistors for proper logical op-

eration.

(Min)

MAX

)

(Max)

MIN

(I )

total maximum output high current for all

outputs tied to pull-up resistor

Where: N (I

)

total maximum input high current for all

inputs tied to pull-up resistor

)

total maximum input low current for all

Connection Diagram

Function Table

Dual-In-Line Package

Inputs

Output

High Logic Level

Low Logic Level

Either Low or High Logic Level

TL/F/6351–1

Order Number DM54LS12J, DM54LS12W,

DM74LS12M or DM74LS12N

See NS Package Number J14A, M14A, N14A or W14B

1995 National Semiconductor Corporation

TL/F/6351

RRD-B30M105/Printed in U. S. A.

12 3 4

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