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DM74ALS390M PDF预览

DM74ALS390M

更新时间: 2024-01-24 18:13:27
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
6页 102K
描述
Dual 4-Bit Decade Counters

DM74ALS390M 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
计数方向:UPJESD-30 代码:R-XDIP-T16
JESD-609代码:e0负载/预设输入:NO
最大I(ol):0.008 A工作模式:ASYNCHRONOUS
功能数量:2端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
子类别:Counters表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

DM74ALS390M 数据手册

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PRELIMINARY  
April 1987  
DM54ALS390/DM74ALS390 Dual 4-Bit Decade Counters  
General Description  
Each of these monolithic counters contains eight master-  
slave flip-flops and additional gating to implement two inde-  
pendent four bit counters in a single package.  
Features  
Y
Switching specifications at 50 pF  
Y
Switching specifications guaranteed over full tempera-  
range  
ture and V  
CC  
Y
Y
Y
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
To use their maximum count length, the B input is connect-  
ed to the QA output. The input count pulses are applied to  
input A and the outputs are as described in the appropriate  
truth table. A symmetrical divide-by-ten count can be ob-  
tained by connecting the QD output to the A input and ap-  
plying the input count to the B input.  
Individual clocks for A and B flip-flops provide dual di-  
vide-by-2 and divide-by-5 counters  
Direct clear for each 4-bit counter  
Connection Diagram  
Function Tables  
BCD Count Sequence  
(See Note 2)  
Output  
Count  
QD  
L
QC  
L
QB  
L
QA  
L
0
1
2
3
4
5
6
7
8
9
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
TL/F/9169–1  
Order Number DM54ALS390J, DM74ALS390M or  
DM74ALS390N  
L
H
H
L
L
H
L
H
H
See NS Package Number J16A, M16A or N16A  
L
L
H
Bi-Quinary (5-2)  
(See Note 3)  
Output  
Count  
QA  
L
QD  
QC  
L
QB  
L
0
1
2
3
4
5
6
7
8
9
L
L
L
L
H
L
L
L
L
H
L
L
H
L
L
H
H
L
L
H
L
L
H
H
H
H
H
L
L
L
H
L
H
H
L
H
L
Note 2: Output QA is connected to input B for BCD count  
Note 3: Output QD is connected to input A for bi-quinary count  
e
e
Low Logic Level  
H
High Logic Level, L  
This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.  
C
1995 National Semiconductor Corporation  
TL/F/9169  
RRD-B30M105/Printed in U. S. A.  

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