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DM54LS85W PDF预览

DM54LS85W

更新时间: 2024-02-06 09:51:54
品牌 Logo 应用领域
美国国家半导体 - NSC 逻辑集成电路
页数 文件大小 规格书
8页 158K
描述
4-Bit Magnitude Comparators

DM54LS85W 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP, FL16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.19JESD-30 代码:R-XDFP-F16
逻辑集成电路类型:MAGNITUDE COMPARATOR端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:DFP
封装等效代码:FL16,.3封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
认证状态:Not Qualified子类别:Arithmetic Circuits
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

DM54LS85W 数据手册

 浏览型号DM54LS85W的Datasheet PDF文件第2页浏览型号DM54LS85W的Datasheet PDF文件第3页浏览型号DM54LS85W的Datasheet PDF文件第4页浏览型号DM54LS85W的Datasheet PDF文件第5页浏览型号DM54LS85W的Datasheet PDF文件第6页浏览型号DM54LS85W的Datasheet PDF文件第7页 
June 1989  
54LS85/DM54LS85/DM74LS85  
4-Bit Magnitude Comparators  
General Description  
e
These 4-bit magnitude comparators perform comparison of  
straight binary or BCD codes. Three fully-decoded decisions  
about two, 4-bit words (A, B) are made and are externally  
available at three outputs. These devices are fully expand-  
able to any number of bits without external gates. Words of  
have a high-level voltage applied to the A  
B input. The  
cascading path is implemented with only a two-gate-level  
delay to reduce overall comparison times for long words.  
Features  
Y
greater length may be compared by connecting compara-  
k
Typical power dissipation 52 mW  
l
e
tors in cascade. The A B, A B, and A  
B outputs of a  
Y
Typical delay (4-bit words) 24 ns  
stage handling less-significant bits are connected to the cor-  
responding inputs of the next stage handling more-signifi-  
cant bits. The stage handling the least-significant bits must  
Y
Alternate Military/Aerospace device (54LS85) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications.  
Connection Diagram  
Dual-In-Line Package  
Order Number 54LS85DMQB,  
54LS85FMQB, 54LS85LMQB,  
DM54LS85J, DM54LS85W,  
DM74LS85M or DM74LS85N  
See NS Package Number E20A,  
J16A, M16A, N16E or W16A  
TL/F/6379–1  
Function Table  
Comparing  
Inputs  
Cascading  
Outputs  
Inputs  
l
k
l
k
e
e
A3, B3  
A2, B2  
A1, B1  
A0, B0  
A
B
A
B
A
B
A
B
A
B
A
B
l
A3 B3  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
k
A3 B3  
l
e
e
e
e
e
e
e
e
e
e
e
e
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
A3  
e
B3  
B3  
B3  
B3  
B3  
B3  
B3  
B3  
B3  
B3  
B3  
B3  
A2 B2  
H
L
k
A2 B2  
H
L
l
e
e
e
e
e
e
e
e
e
e
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
A2  
B2  
B2  
B2  
B2  
B2  
B2  
B2  
B2  
B2  
B2  
A1 B1  
H
L
k
A1 B1  
H
L
l
e
e
e
e
e
e
e
e
A1  
A1  
A1  
A1  
A1  
A1  
A1  
A1  
B1  
B1  
B1  
B1  
B1  
B1  
B1  
B1  
A0 B0  
H
L
k
A0 B0  
H
L
e
e
e
e
e
e
A0  
A0  
A0  
A0  
A0  
A0  
B0  
B0  
B0  
B0  
B0  
B0  
H
L
H
L
L
H
L
L
H
H
L
L
X
H
L
X
H
L
L
L
L
L
L
H
H
e
e
H
High Level, L  
Low Level, X  
Don’t Care  
C
1995 National Semiconductor Corporation  
TL/F/6379  
RRD-B30M105/Printed in U. S. A.  

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