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DM54LS283W PDF预览

DM54LS283W

更新时间: 2024-01-19 10:21:08
品牌 Logo 应用领域
美国国家半导体 - NSC 运算电路逻辑集成电路
页数 文件大小 规格书
8页 160K
描述
4-Bit Binary Adders with Fast Carry

DM54LS283W 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:CERAMIC, FP-16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.26Is Samacsys:N
其他特性:FULL ADDER; WITH INTERNAL CARRY LOOKAHEAD; PERMITS RIPPLE CARRY CASCADING系列:LS
JESD-30 代码:R-CDFP-F16JESD-609代码:e0
长度:9.6645 mm逻辑集成电路类型:ADDER/SUBTRACTOR
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DFP
封装等效代码:FL16,.3封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):26 ns
认证状态:Not Qualified座面最大高度:2.032 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.604 mmBase Number Matches:1

DM54LS283W 数据手册

 浏览型号DM54LS283W的Datasheet PDF文件第2页浏览型号DM54LS283W的Datasheet PDF文件第3页浏览型号DM54LS283W的Datasheet PDF文件第4页浏览型号DM54LS283W的Datasheet PDF文件第5页浏览型号DM54LS283W的Datasheet PDF文件第6页浏览型号DM54LS283W的Datasheet PDF文件第7页 
June 1989  
54LS283/DM54LS283/DM74LS283  
4-Bit Binary Adders with Fast Carry  
General Description  
Features  
Y
Full-carry look-ahead across the four bits  
These full adders perform the addition of two 4-bit binary  
numbers. The sum (R) outputs are provided for each bit and  
the resultant carry (C4) is obtained from the fourth bit.  
These adders feature full internal look ahead across all four  
bits. This provides the system designer with partial look-  
ahead performance at the economy and reduced package  
count of a ripple-carry implementation.  
Y
Systems achieve partial look-ahead performance with  
the economy of ripple carry  
Y
Typical add times  
Two 8-bit words 25 ns  
Two 16-bit words 45 ns  
Y
Y
Typical power dissipation per 4-bit adder 95 mW  
Alternate Military/Aerospace device (54LS283) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications.  
The adder logic, including the carry, is implemented in its  
true form meaning that the end-around carry can be accom-  
plished without the need for logic or level inversion.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6421–1  
Order Number 54LS283DMQB, 54LS283FMQB, 54LS283LMQB,  
DM54LS283J, DM54LS283W, DM74LS283M or DM74LS283N  
See NS Package Number E20A, J16A, M16A, N16E or W16A  
C
1995 National Semiconductor Corporation  
TL/F/6421  
RRD-B30M105/Printed in U. S. A.  

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