If small wire cables are used, good engineering practice is to
calculate the wire resistance of the ground and the +5 volt
wires. More than 0.2 volt drop (at 100 ma per digit) should be
avoided, since this loss is in addition to any inaccuracies or load
regulation of the power supply.
Subroutine to Load an 8-digit Display using the DLO4135/
DLG4137
; DATA IN RAM 10H-17H
(MSD-LSD)
INIT
ORL P1,#0FFH
ORL P2,#00H
MOV R1,#OFH
; PORT 1 ALL HIGH (WRITE)
; PORT 2 ALL LOW (DATA)
; RAM ADDRESS—1
The 5 volt power supply for the DLO4135/DLG4137 should be
the same one supplying the V to all logic devices. If a separate
CC
MOV R2,#0FEH ; WRITE PULSE
power supply must be used, then local buffers should be used
on all the inputs. These buffers should be powered from the dis-
play power supply. This precaution is to avoid line transients or
MOV R3,#08H
START: INC R1
DATA: MOV A,@R1
OUTL P2,A
; COUNTER
; INCREMENT RAM POINTER
; FETCH DATA FROM RAM
; LOAD PORT 2
any logic signals to be higher than V during power up.
CC
MOV A,R2
; RECALL WRITE
; SHIFT A TO NEXT WRITE
; SAVE WRITE
Figure 5. Block diagram of the Intel 8031 controller
RR
A
D Ø
D 7
MOV R2,A
WRITE: OUTL P1,A
; SEND WRITE PULSE
; WAIT
x
x
x
x
x
MOV A,#OFFH
OUTL P1,A
DJNZ R3,START
RET
; RESET WRITE PULSE
; LOAD COMPLETE?
; RETURN TO MAIN PROGRAM
BUFFER
P3.0
P3.1
P3.2
P3.6
Figure 7. Block diagram for 8-digit DLO4135/DLG4137
8
PØ
8031
PSEN
Eight DLX413X
8
8
3
ALE
8080
Data
8
A0-A7
DECODER
or
LATCH
I/OW
OE
8085
System
A0
A1
A2
EPROM
27xx
Address
Interfacing
For an eight digit display using the DLO4135/DLG4137, inter-
facing to a single chip microprocessor such as the 8748, is easy
and straight forward. One approach may be to dedicate one
port for the seven data signals and another 8-bit port for the
write signals. The schematic is shown in Figure 6.
Routine for an 8-Digit Display using the DLO4135/DLG4137
and 8085 or 8080 Microprocessor
; DATA TO BE DISPLAYED IS IN
; A0 (LSD) THRU A7 (MSD)
;
; DISPLAY ADDRESS C00X
I/O or Memory Mapped System
; LSD IS RIGHT MOST DIGIT
;
For a memory mapped system using a processor such as the
8080 or 8085, the interfacing is also straight-forward. Each dis-
play is treated as a memory location with its own address, like
another I/O or RAM location. See Figure 7.
; DOES NOT SAVE REG A,B,H,L,D,E
;
; DATA ADDRESS LOCATION
; DISPLAY ADDRESS
LOCATION
DADD EQU 0A000H
DPAD EQU 0C000H
Figure 6. DLO4135/DLG4137 with 8748
LEN
EQU 08H
100H
; DISPLAY LENGTH
;
8748
P1
P2
ORG
;
6 5 4 3 2 1 0
7
6
5
4
3
2
1
0
DISP: LXI
LXI
H,DADD
D,DPAD
B,LEN
; LOAD DATA ADDRESS
; LOAD DISPLAY ADDRESS
; LOAD DISPLAY LENGTH
; GET DATA
; XCHG H/L & D/E
; LOAD DISPLAY FROM REG A
; RESTORE H/L & D/E
D0
D1
D2
D3
D4
D5
D6
MVI
DLO 4135
DLG 4137
DISP1: MOV A,M
XCHG
MOV M,A
XCHG
INX
INX
DCR
JNZ
RET
D
H
B
; INCREMENT DISPLAY ADDRESS
; INCREMENT DATA ADDRESS
; DECREMENT LENGTH COUNTER
; END OF DISPLAY?
+
DISP1
; RETURN TO MAIN PROGRAM
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
Appnote 28
3
May 31, 2000-13