ELECTRICAL CHARACTERISTICS
VREF = +10V, VOUT 1 = 0V, and ACOM = DCOM, unless otherwise specified.
DAC7545
VDD = +5V
VDD = +15V
(1)
(1)
PARAMETER
GRADE
TA = +25°C TMAX-TMIN
TA = +25°C TMAX-TMIN
UNITS TEST CONDITIONS/COMMENTS
STATIC PERFORMANCE
Resolution
Accuracy
All
J
K
L
GL
J
K
L
GL
J
K
12
±2
±1
±1/2
±1/2
±4
±1
±1
±1
12
±2
±1
±1/2
±1/2
±4
±1
±1
±1
12
±2
±1
±1/2
±1/2
±4
±1
±1
±1
±25
±15
±10
±6
12
±2
±1
±1/2
±1/2
±4
±1
±1
±1
±25
±15
±10
±7
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Differential Nonlinearity
10-Bit Monotonic, TMIN to TMAX
10-Bit Monotonic, TMIN to TMAX
12-Bit Monotonic, TMIN to TMAX
12-Bit Monotonic, TMIN to TMAX
DAC register loaded with FFFH.
Gain error is adjustable using
the circuits in Figures 2 and 3.
(2)
Gain Error (with internal RFB
)
±20
±10
±5
±20
±10
±6
L
GL
±2
±3
Gain Temperature Coefficient(3)
(∆Gain/∆Temperature)
All
±5
±5
±10
±10
ppm/°C Typical Value is 2ppm/°C
for VDD = +5
DC Supply Rejection(3)
(∆Gain/∆VDD
Output Leakage Current at Out 1
)
All
0.015
10
0.03
50
0.01
10
0.02
50
%/%
nA
∆VDD ± 5%
DB0-DB11 = 0V; WR, CS = 0V
J, K, L, GL
DYNAMIC PERFORMANCE
Current Settling Time(3)
All
2
2
2
2
µs
To 1/2 LSB. Out 1 Load = 100Ω
DAC output measured from
falling edge of WR. CS = 0V.
Propagation Delay(3) (from digital input
change to 90% of final analog output)
Glitch Energy
All
300
400
5
250
250
5
ns
Out 1 Load = 100Ω. CEXT = 13pF(4)
All
All
nV-s(5) VREF = ACOM
AC Feedback at IOUT 1
5
5
mVp-p(5) VREF = ±10V, 10kHz Sine Wave
REFERENCE INPUT
Input Resistance (pin 19 to AGND)
All
7
25
7
25
7
25
7
25
kΩ(6)
kΩ
Input Resistance TC = 300ppm/°C(5)
AC OUTPUTS
Output Capacitance(3): COUT 1
COUT 2
All
All
70
200
70
200
70
200
70
200
pF
pF
DB0-DB11 = 0V; WR, CS = 0V
DB0-DB11 = VDD; WR, CS = 0V
DIGITAL INPUTS
V
IH (Input HIGH Voltage)
VIL (Input LOW Voltage)
IN (Input Current)(7)
All
All
All
All
All
2.4
0.8
±1
5
2.4
0.8
±10
5
13.5
1.5
±1
5
20
13.5
1.5
±10
5
V(6)
V
µA
pF
pF
I
VIN = 0V or VDD
VIN = 0V
VIN = 0V
Input Capacitance(3): DB0-DB11
WR, CS
20
20
20
SWITCHING CHARACTERISTICS(8)
Chip Select to Write Setup Time, tCS
All
280
200
0
250
175
140
100
10
380
270
0
400
280
210
150
10
180
120
0
160
100
90
200
150
0
240
170
120
80
ns(6)
ns(5)
ns(6)
ns(6)
ns(5)
ns(6)
ns(5)
ns(6)
See Timing Diagram
Chip Select to Write Hold Time, tCH
Write Pulse Width, tWR
All
All
tCS ≥ tWR, tCH ≥ 0
Data Setup Time, tDS
All
All
60
10
Data Hold Time, tDH
10
POWER SUPPLY, IDD
All
All
All
2
100
10
2
500
10
2
100
10
2
500
10
mA
µA
µA(5)
All Digital Inputs VIL or VIH
All Digital Inputs 0V or VDD
All Digital Inputs 0V or VDD
NOTES: (1) Temperature ranges—J, K, L, and GL: –40°C to +85°C. (2) This includes the effect of 5ppm max, gain TC. (3) Ensured but not tested. (4) DB0-DB11 = 0V
to VDD or VDD to 0V. (5) Typical. (6) Minimum. (7) Logic inputs are MOS gates. Typical input current (+25°C) is less than 1nA. (8) Sample tested at +25°C to ensure
compliance.
DAC7545
SBAS150A
3
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