DAC53204W, DAC63204W
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ZHCSRA2 –DECEMBER 2022
5 Pin Configuration and Functions
1
2
3
4
A
B
C
D
VREF
OUT3
OUT2
GPIO/SDO
VDD
AGND
CAP
FB3
FB0
FB2
FB1
SCL/SYNC
A0/SDI
OUT0
OUT1
SDA/SCLK
Not to scale
图5-1. YBH Package, 16-pin DSBGA (Top View)
表5-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
External reference input. Connect a capacitor (approximately 0.1 μF) between VREF and AGND.
Use a pullup resistor to VDD when the external reference is not used. Do not ramp up this pin before
VDD. In case an external reference is used, make sure the reference ramps up after VDD.
A1
VREF
Power
A2
A3
OUT3
OUT2
Output
Output
Analog output voltage from DAC channel 3.
Analog output voltage from DAC channel 2.
General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS.
A4
GPIO/SDO Input/Output For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor. If unused,
connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD.
B1
B2
VDD
FB3
Power
Input
Supply voltage.
Voltage feedback pin for channel 3. In voltage-output mode, connect to OUT3 for closed-loop amplifier
output. In current-output mode, keep the FB3 pin unconnected to minimize leakage current.
Voltage feedback pin for channel 2. In voltage-output mode, connect to OUT2 for closed-loop amplifier
output. In current-output mode, keep the FB2 pin unconnected to minimize leakage current.
B3
FB2
Input
I2C serial interface clock or SPI chip select input. Connect this to the IO voltage using an external
pullup resistor. This pin can ramp up before VDD.
B4
C1
C2
SCL/SYNC
AGND
Output
Ground
Input
Ground reference point for all circuitry on the device.
Voltage feedback pin for channel 0. In voltage-output mode, connect to OUT0 for closed-loop amplifier
output. In current-output mode, keep the FB0 pin unconnected to minimize leakage current.
FB0
Voltage feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-loop amplifier
output. In current-output mode, keep the FB1 pin unconnected to minimize leakage current.
C3
C4
D1
FB1
A0/SDI
CAP
Input
Input
Address configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (节7.5.2.2.1).
For SDI, this pin need not be pulled up or pulled down. This pin can ramp up before VDD.
External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between
CAP and AGND.
Power
D2
D3
OUT0
OUT1
Output
Output
Analog output voltage from DAC channel 0.
Analog output voltage from DAC channel 1.
Bidirectional I2C serial data bus or SPI clock input. Connect this pinto the IO voltage using an external
pullup resistor in I2C mode. This pin can ramp up before VDD.
D4
SDA/SCLK Input/Output
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