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DAC1210LCJ PDF预览

DAC1210LCJ

更新时间: 2024-01-03 20:42:26
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器模数转换器
页数 文件大小 规格书
18页 362K
描述
12-Bit, uP Compatible, Double-Buffered D to A Converters

DAC1210LCJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP24,.6Reach Compliance Code:unknown
风险等级:5.92转换器类型:D/A CONVERTER
输入位码:OFFSET BINARY, COMPLEMENTARY OFFSET BINARYJESD-30 代码:R-XDIP-T24
JESD-609代码:e0最大线性误差 (EL):0.05%
位数:12功能数量:1
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP24,.6
封装形状:RECTANGULAR封装形式:IN-LINE
电源:12/15 V子类别:Other Converters
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

DAC1210LCJ 数据手册

 浏览型号DAC1210LCJ的Datasheet PDF文件第1页浏览型号DAC1210LCJ的Datasheet PDF文件第2页浏览型号DAC1210LCJ的Datasheet PDF文件第4页浏览型号DAC1210LCJ的Datasheet PDF文件第5页浏览型号DAC1210LCJ的Datasheet PDF文件第6页浏览型号DAC1210LCJ的Datasheet PDF文件第7页 
Electrical Characteristics (Continued)  
e
Note 13); all other limits T  
e
V
10.000 V , V  
DC CC  
11.4 V  
T
to 15.75 V  
DC  
e
25 C.  
unless otherwise noted. Boldface limits apply from T  
to T (see  
MAX  
REF  
DC  
MIN  
e
§
A
J
Tested  
Design  
Limit  
See  
Typ  
Symbol  
Parameter  
Conditions  
Limit  
Units  
Note  
(Note 10)  
(Note 5)  
(Note 6)  
AC CHARACTERISTICS  
e
e
e
e
t
t
Current Setting Time  
V
V
0V, V  
0V, V  
5V  
5V  
1.0  
50  
ms  
s
IL  
IH  
Write and XFER  
Pulse Width Min.  
320  
W
IL  
IH  
8
320  
e
e
e
e
e
e
e
e
t
t
t
t
Data Setup Time Min.  
V
IL  
V
IL  
V
IL  
V
IL  
0V, V  
0V, V  
0V, V  
0V, V  
5V  
5V  
5V  
5V  
70  
30  
60  
0
320  
DS  
DH  
CS  
CH  
IH  
IH  
IH  
IH  
320  
Data Hold Time Min.  
90  
ns  
90  
Control Setup Time Min.  
Control Hold Time Min.  
320  
320  
10  
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating  
the device beyond its specified operating conditions.  
Note 2: All voltages are measured with respect to GND, unless otherwise specified.  
Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify  
the power dissipation) removes concern for heat sinking.  
d
Note 4: Both I  
and I  
must go to ground or the virtual ground of an operational amplifier. The linearity error is degraded by approximately V  
V
. For  
REF  
OUT1  
e
OUT2  
10V then a 1 mV offset, V , on I  
OS  
example, if V  
REF  
or I  
will introduce an additional 0.01% linearity error.  
OUT2  
OS OUT1  
Note 5: Tested and guaranteed to National’s AOQL (Average Outgoing Quality Level).  
e
Note 6: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Guaranteed for V  
a
10V to 10V.  
11.4V to 15.75V  
CC  
e
b
and V  
REF  
Note 7: The unit FSR stands for full-scale range. Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular  
value to indicate the true performance of the part. The Linearity Error specification of the DAC1208 is 0.012% of FSR(max). This guarantees that after  
V
REF  
performing a zero and full-scale adjustment, the plot of the 4096 analog voltage outputs will each be within 0.012%  
c
V
of a straight line which passes through  
REF  
zero and full-scale. The unit ppm of FSR(parts per million of full-scale range) and ppm of FS(parts per million of full-scale) are used for convenience to define specs  
6
e
output voltage quantity. For example, the gain error tempco spec of 6 ppm of FS/ C represents a worst-case full-scale gain error change with temperature from  
of very small percentage values, typical of higher accuracy converters. In this instance, 1 ppm of FSR  
g
V
/10 is the conversion factor to provide an actual  
REF  
§
b
6
3
/10 )(125 C) or 0.75 (10 ) V  
b
a
40 C to 85 C of (6)(V  
g
g
g
which is 0.075% of V .  
REF  
§
§
§
Note 8: This spec implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t ) of 320 ns. A typical part will operate with t of only  
REF  
REF  
W
and t to apply.  
S
W
100 ns. The entire write pulse must occur within the valid data interval for the specified t , t , t  
W DS DH  
Note 9: To achieve this low feedthrough in the D package, the user must ground the metal lid. If the lid is left floating the feedthrough is typically 6 mV.  
Note 10: Typicals are at 25 C and represent the most likely parametric norm.  
§
Note 11: A 10 nA leakage current with R  
b
9
3
c
e
e
c
10V corresponds to a zero error of (10 10  
c c  
20 10 ) 100% 10V or 0.002% of FS.  
20k and V  
Fb  
REF  
Note 12: Human body model, 100 pF discharged through a 1.5 kX resistor.  
b
Note 13: Tested limit for 1 suffix parts applies only at 25 C.  
§
Connection Diagrams  
Dual-In-Line Package  
Dual-In-Line Package  
TL/H/5690–2  
See Ordering Information  
3

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