DAC08
10.000V
B1 B2 B3 B4 B5 B6 B7 B8
E
E
O
O
MSB
LSB
POS. FULL RANGE
POS. FULL RANGE –LSB
ZERO-SCALE +LSB
ZERO-SCALE
ZERO-SCALE –LSB
NEG. FULL-SCALE +LSB
NEG. FULL-SCALE
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
–9.920 +10.000
–9.840 +9.920
–0.080 +0.160
10.000k⍀
10.000k⍀
B1 B2 B3 B4 B5 B6 B7 B8
0.000
+0.080
I
E
E
O
O
O
4
2
I
(+) = 2.000mA
+0.080 0.000
+9.920 –9.840
+10.000 –9.920
REF
14
I
O
Figure 10. Basic Bipolar Output Operation
LOW T.C.
4.5k⍀
R
REF
I
I
O
14
15
V
REF
10V
4
2
14
15
I
(+) 2mA
1V
REF
O
39k⍀
R15
–V
REF
10k⍀
POT
NOTE
–V
R
REF
APPROX
I
R
SETS I ; R15 IS FOR
FS
REF
FS
5k⍀
REF
BIAS CURRENT CANCELLATION.
Figure 11. Recommended Full-Scale Adjustment Circuit
Figure 12. Basic Negative Reference Operation
10k⍀
5.0k⍀
15V
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
+15V
2
5.000k⍀
5.0k⍀
6
5
10V
B1 B2 B3 B4 B5 B6 B7 B8
E
O
I
I
O
O
V
O
4
2
POS. FULL RANGE
ZERO-SCALE
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1 +4.960
0 0.000
1 –4.960
0 –5.000
E
OP711
O
REF01*
NEG. FULL-SCALE +1 LSB 0
NEG. FULL-SCALE 0
V+ V–
C
V
C
LC
4
*OR ADR01
+15V –15V
–15V
Figure 13. Offset Binary Operation
R
L
I
I
O
E
OP711
O
L
4
I
I
O
4
2
E
O
OP711
O
FR
2
R
O
L
255
256
FR
L
I
=
I
REF
FR
255
256
I
=
I
REF
FR
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT INVERTING INPUT OF OP AMPTO I (PIN 2); CONNECT I (PIN 4)TO
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT NONINVERTING INPUT OF OP AMPTO I (PIN 2); CONNECT I (PIN 4)
O
O
O
O
GROUND.
TO GROUND.
Figure 14. Positive Low Impedance Output Operation
Figure 15. Negative Low Impedance Output Operation
CMOS, HTL, NMOS
V
=V
1.4V
LC
TH
ECL
15V CMOS
= 7.6V
V+
V
TH
15V
TTL, DTL
= 1.4V
V
TH
13k⍀
20k⍀
9.1k⍀
6.2k⍀
V
2N3904
3k⍀
2N3904
LC
“A”
“A”
2N3904
2N3904
V
LC
0.1F
3k⍀
TO PIN 1
TO PIN 1
1
39k⍀
20k⍀
V
V
LC
LC
R3
400A
6.2k⍀
–5.2V
TEMPERATURE COMPENSATINGV
CIRCUITS
LC
Figure 16. Interfacing with Various Logic Families
–9–
REV. B