Converter Electrical Characteristics (Continued)
e
e
e
e
10 MHz unless otherwise specified. Boldface limits apply for T
e
1.4V, R 2 kX (R is the load resistor on
The following specifications apply for AV
DV
CC
5V, V
2.65V, V
CC
REF
BIAS
L
L
e
the analog outputs – pins 1, 11, 14, and 19) and f
CLK
A
e
e
25 C.
T
from T
to T
. All other limits apply for T
MAX A
§
J
MIN
Typical
(Note 3)
Limit
(Note 4)
Units
(Limits)
Symbol
Parameter
Conditions
AC ELECTRICAL CHARACTERISTICS (Continued)
t
t
t
t
Output Hi-Z to Valid 1
Output Hi-Z to Valid 0
CS to Output Hi-Z
37
42
ns (max)
ns (max)
ns (max)
ns (max)
CZ1
CZ0
1H
10 kX with 60 pF
10 kX with 60 pF
130
117
CS to Output Hi-Z
0H
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Converter Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not
operated under the listed test conditions.
Note 2: All voltages are measured with respect to ground, unless otherwise specified.
a) the absolute value of current at that pin should be limited
k
l
V
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN
to 5 mA or less.
GND or V
IN
IN
Note 4: The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by
(package junction to ambient thermal resistance), and (ambient temperature). The maximum allowable power dissipation at any temperature is
T
(maximum junction temperature), H
JA
Jmax
T
A
e
packages and versions of the DAC0854.
b
T
P
Dmax
(T
)/H or the number given in the Absolute Maximum Ratings, whichever is lower. The table below details T and H for the various
JA Jmax JA
Jmax
A
Part Number
T
( C)
§
H
( C/W)
§
Jmax
JA
DAC0854BIN, DAC0854CIN
DAC0854BIJ, DAC0854CIJ
DAC0854BIWM, DAC0854CIWM
DAC0854CMJ/883
125
125
125
150
46
53
64
53
Note 6: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 7: See AN450 ‘‘Surface Mounting Methods and Their Effect on Production Reliability’’ of the section titled ‘‘Surface Mount’’ found in any current Linear
Databook for other methods of soldering surface mount devices.
e
Note 8: Typicals are at T
25 C and represent most likely parametric norm.
§
Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
J
Note 10: A monotonicity of 8 bits for the DAC0854 means that the output voltage changes in the same direction (or remains constant) for each increase in the input
code.
Note 11: Integral linearity error is the maximum deviation of the output from the line drawn between zero and full-scale (excluding the effects of zero error and full-
scale error).
e
e
Note 12: Full-scale error is measured as the deviation from the ideal 2.800V full-scale output when V
Note 13: Full-scale error tempco and zero error tempco are defined by the following equation:
2.650V and V
1.400V.
REF
BIAS
6
10
b
Error (T
)
Error (T
)
MIN
MAX
e
Error tempco
b
V
T
T
Ð
( Ð
(
Note 16: Positive or negative settling time is defined as the time taken for the output of the DAC to settle to its final full-scale or zero output to within 0.5 LSB.
SPAN
MAX
MIN
where Error (T
MAX
) is the zero error or full-scale error at T
(in volts), and Error (T
) is the zero error or full-scale error at T
(in volts); V
is the output
MAX
and V
MIN
MIN
SPAN
voltage span of the DAC0854, which depends on V
BIAS
.
REF
e
e
BIAS
Note 14: Zero error is measured as the deviation from the ideal 0.310V output when V
2.650V, V
1.400V, and the digital input word is all zeros.
REF
Note 15: Power Supply Sensitivity is the maximum change in the offset error or the full-scale error when the power supply differs from its optimum 5V by up to
e
0.25V (5%). The load resistor R
5 kX.
L
g
This time shall be referenced to the 50% point of the positive edge of CS, which initiates the update of the analog outputs.
Note 17: Digital crosstalk is the glitch measured on the output of one DAC while applying an all 0s to all 1s transition at the input of the other DACs.
Note 18: All DACs have full-scale outputs latched and DI is clocked with no update of the DAC outputs. The glitch is then measured on the DAC outputs.
Note 19: Clock feedthrough is measured for each DAC with its output at full-scale. The serial clock is then applied to the DAC at a frequency of 10 MHz and the
glitch on each DAC full-scale output is measured.
Note 20: Channel-to-channel isolation is a measure of the effect of a change in one DAC’s output on the output of another DAC. The V
of the first DAC is varied
REF
between 1.4V and 2.65V at a frequency of 15 kHz while the change in full-scale output of the second DAC is measured. The first DAC is loaded with all 0s.
Note 21: Glitch energy is the difference between the positive and negative glitch areas at the output of the DAC when a 1 LSB digital input code change is applied
to the input. The glitch energy will have its largest value at one of the three major transitions. The peak value of the maximum glitch is separately specified.
e
of this signal imposed on a full-scale output of the DAC under consideration.
Note 22: Power Supply Rejection Ratio is measured by varying AV
CC
DV between 4.75V and 5.25V with a frequency of 10 kHz and measuring the proportion
CC
Note 23: The bandgap reference tempco is defined by the following equation:
6
10
b
V
(T
REF MAX
)
V
(T
REF MIN
)
e
Tempco
b
T
MIN
V
(T
REF ROOM
)
T
Ð
( Ð
(
MAX
e
where T
25 C, V
(T
REF MAX
) is the reference output at T
, and similarly for V
(T
REF MIN
) and V
(T
REF ROOM
).
§
Note 24: A Military RETS specification is available upon request.
ROOM
MAX
4
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