5秒后页面跳转
DAC-1025-QL PDF预览

DAC-1025-QL

更新时间: 2022-02-26 11:13:06
品牌 Logo 应用领域
达特尔 - DATEL /
页数 文件大小 规格书
6页 431K
描述
10-Bit, 250MSPS, Low-Power D/A Converters

DAC-1025-QL 数据手册

 浏览型号DAC-1025-QL的Datasheet PDF文件第1页浏览型号DAC-1025-QL的Datasheet PDF文件第2页浏览型号DAC-1025-QL的Datasheet PDF文件第3页浏览型号DAC-1025-QL的Datasheet PDF文件第5页浏览型号DAC-1025-QL的Datasheet PDF文件第6页 
DAC-1025  
10-Bit, 250MSPS, Low-Power D/A Converters  
TECHNICAL NOTES  
Humidity Susceptibility  
PIN DESCRIPTIONS  
Plastic mold compounds that are used to house ICs can absorb moisture.When these  
devices are exposed tohumidity the plastic package can undergo slight changes that can  
apply pressure to the internal die. Stresses placed on a precision data converters can cause  
DIBOHFTꢀJOꢀJUTꢀQFSGPSNBODFꢀJOꢀUIFꢀPSEFSꢀPGꢀꢋꢃꢃQQNꢊꢀ5IFꢀGVMMZꢀIFSNFUJDꢀQBDLBHFꢀP ꢀFSFEꢀGPSꢀ  
UIFꢀo2-ꢀBOEꢀꢇꢅꢅꢈꢀWFSTJPOTꢀBSFꢀOPUꢀB ꢀFDUFEꢀCZꢀIVNJEJUZꢆꢀBOEꢀBSFꢀUIFSFGPSFꢀNPSFꢀTUBCMFꢀJOꢀ  
environments where humidity is a concern.  
PIN  
PIN NAME  
DESCRIPTION  
1 -10 BIT 1 (MSB) through B10 (LSB) Digital Data input bits. B1 (MSB), B10 (LSB).  
11, 12,  
13,14  
19,25  
15  
DGND  
NC  
Digital Ground  
No Connection. For noise rejection may be tied  
to AGND.  
Control pin to power-down the DAC. Sleep = HI,  
On = LO. Internal 20µA active pull-down current.  
Connect to AGND to enable internal 1.24V  
reference. Connect to AVDD to disable internal  
reference.  
Reference voltage output when using internal  
1.24V reference  
Input pin when supplying external reference.  
Full Scale current adjustment (gain). Use resistor  
to AGND to set current (see technical notes).  
External capacitor to AGND helps to reduce  
bandwidth.  
SHTDWN  
Board Mounting Considerations  
For applications requiring the highest accuracy, attention should be paid to the board  
mounting location of SE and SM devices.These models use a plasticTSSOP package  
that could subject the die to mild stresses when the printed circuit board is cooled or  
heated. Placing the device in areas subject to slight twisting may cause die stresses and  
consequentlydegradation in the accuracyof the converter. It is preferred that the device  
be placed in the center of the PCBor near the edge of the shortest side where stresses due  
UPꢁ ꢁFYJOHꢁBSFꢁSFEVDFEꢆꢁ.PVOUJOHꢁUIFꢁEFWJDFꢁJOꢁBꢁꢁDVUPVUꢁBMTPꢁNJOJNJ[FTꢁ ꢁFYꢆꢁ.PVOUJOHꢁUIFꢁ  
EFWJDFꢁPOꢁBOꢁFYUSFNFMZꢁꢁUIJOꢁ1$#ꢁPSꢁ ꢁFYQSJOUꢁXJMMꢁJODSFBTFꢁUIFꢁQPUFOUJBMꢁGPSꢁMPTTꢁPGꢁBDDVSBDZꢁ  
EVFꢀUPꢀTUSFTTꢊꢀ5IFꢀ$-$$ꢀQBDLBHFꢀP ꢀFSFEꢀGPSꢀꢄ2-ꢀBOEꢀꢇꢅꢅꢈꢀEFWJDFTꢀFMJNJOBUFTꢀUIFꢀQPUFOUJBMꢀ  
for die stress.  
16  
REFSEL  
17  
18  
REFI/O  
GAINADJ  
23  
20  
COMP  
AGND  
Analog Ground  
Complimentary output current. Full scale is  
attained when digital inputs are at all 0's.  
True output current. Full scale is attained when  
digital inputs are at all 1's.  
Supply for analog circuitry+2.7V to +3.6V  
(+3.0V to +3.6V recommended).  
21  
22  
IOUTB  
IOUTA  
Board Assembly Considerations  
Precision converters provide high accuracyover temperature extremes, but some PC board  
assemblyprecautions are necessary. Changes in DC parameters can be expected with  
1CꢀGSFFꢁSF ꢁPXꢁQSP ꢁMFTꢁPSꢁXBWFꢁTPMEFSꢁPOꢁNVMUJMBZFSꢁ'3ꢑꢁ1$ꢁCPBSETꢆꢁ1SFDBVUJPOTꢁTIPVMEꢁCFꢁ  
UBLFOꢁUPꢁBWPJEꢁFYDFTTJWFꢁIFBUꢁPSꢁFYUFOEFEꢁFYQPTVSFꢁUPꢁIJHIꢁSF ꢁPXꢁPSꢁXBWFꢁTPMEFSꢁUFNQFSBꢀ  
tures, this may reduce device initial accuracy.  
24  
26  
27  
AVDD  
DGND  
DVDD  
Digital Ground  
Supply for digital circuitry +2.7V to +3.6V  
Rising edge of clock latchesdata into input  
registers  
28  
CLK  
GLOSSARY OF SPECIFICATIONS  
DIFFERENTIAL LINEARITY ERROR:The maximum deviation of any quantum (LSB  
change) in the transfer function of a data converter from its ideal size of FSR/2n.  
108&3ꢁ4611-:ꢁ3&+&$5*0/ꢁ3"5*0ꢁŷ1433Ÿ: The output change in a data converter  
caused by a change in power supply voltage. Power supply sensitivity is generally speci-  
ꢁFEꢁJOꢁꢒꢓ7ꢁPSꢁJOꢁꢒꢓꢒꢁTVQQMZꢁDIBOHFꢆ  
DIFFERENTIAL LINEARITY TEMPCO:5IFꢀDIBOHFꢀJOꢀEJ ꢀFSFOUJBMꢀMJOFBSJUZꢀFSSPSꢀXJUIꢀ  
temperature for a data converter, expressed in ppm/°C of FSR (Full Scale Range).  
REFERENCE INPUT MULTIPLYING BANDWIDTH:The -3dB reduction in the output  
when applying a sinusoidal voltage to the external reference (digital inputs are set to all  
1s).The frequency is increased until the amplitude of the output waveform is -3dB of its  
original value.  
GAIN ERROR:5IFꢀEJ ꢀFSFODFꢀJOꢀTMPQFꢀCFUXFFOꢀUIFꢀBDUVBMꢀBOEꢀJEFBMꢀUSBOTGFSꢀGVODUJPOTꢀGPSꢀ  
a data converter or other circuit. It is expressed as a percent of analog magnitude.  
GAIN TEMPCO:The change in gain (or scale factor) with temperature for a data con-  
verter or other circuit, generally expressed in ppm/°C.  
SETTLINGTIME: The time elapsed from the application of a full scale step input to a cir-  
DVJUꢁUPꢁUIFꢁUJNFꢁXIFOꢁUIFꢁPVUQVUꢁIBTꢁFOUFSFEꢁBOEꢁSFNBJOFEꢁXJUIJOꢁBꢁTQFDJ ꢁFEꢁFSSPSꢁCBOEꢁ  
BSPVOEꢁJUTꢁ ꢁOBMꢁWBMVFꢆꢁ5IJTꢁUFSNꢁJTꢁBOꢁJNQPSUBOUꢁTQFDJ ꢁDBUJPOꢁGPSꢁPQFSBUJPOBMꢁBNQMJ ꢁFSTꢂꢁ  
analog multiplexers, and D/A converters.  
INTEGRAL LINEARITY ERROR:The maximum deviation of a data converter transfer  
GVODUJPOꢀGSPNꢀUIFꢀJEFBMꢀTUSBJHIUꢀMJOFꢀXJUIꢀP ꢀTFUꢀBOEꢀHBJOꢀFSSPSTꢀ[FSPFEꢊꢀ*UꢀJTꢀHFOFSBMMZꢀ  
expressed in LSB's or in percent of FSR.  
TOTAL HARMONIC DISTORTION:ꢁ5IFꢁSBUJPꢁPGꢁUIFꢁSNTꢁTVNꢁPGꢁUIFꢁ ꢁSTUꢁꢏꢁIBSNPOJDTꢁUPꢁUIFꢁ  
rms of the fundamental signal, usually expressed in dB  
INTERNAL REFERENCE VOLTAGE DRIFT:The maximum deviation from the measured  
value at room temperature as compared with the value measured at eitherTmin orTmax.  
GLITCH AREA:The transientappearing at the output when the input switches from  
one code to another.Typically the worst case is found at the MSB code transition. It is  
measured as the area under the overshoot portion of the curve and is expressed as a  
7PMUꢀ5JNFꢁTQFDJ ꢁDBUJPOꢆ  
OUTPUT COMPLIANCE RANGE:The allowable MaximumVoltage at the output of a  
D/A.  
OFFSET ERROR:The deviation from the ideal at analog zero output  
SPURIOUS FREE DYNAMIC RANGE (SFDR):The largest harmonic, spurious frequency  
or noise component in a signal FFT. Itis expressed in dbwith respect tothe fundamental  
frequency.  
OFFSET DRIFT:The change with temperature ofanalog zero for a data converter operat-  
ing in the bipolar mode. Itis generally expressed in ppm/°C of FSR.  
%"5&-ꢀꢁ*ODꢂꢁꢃꢃꢁ$BCPUꢁ#PVMFWBSEꢀꢁ.BOT ꢁFMEꢀꢁ."ꢁꢄꢅꢄꢆꢇꢁ64"ꢁ tꢁ 5FMꢈꢁꢉꢊꢄꢇꢋꢌꢍꢆꢎꢊꢃꢏꢃꢁ tꢁ XXXꢂEBUFMꢂDPNꢁ tꢁ FꢎNBJMꢈꢁIFMQ!EBUFMꢂDPN  
01 Feb 2016 MDA_DAC-1025.C01.D1 Page4 of 6  

与DAC-1025-QL相关器件

型号 品牌 描述 获取价格 数据表
DAC-1025SE DATEL 10-Bit, 250MSPS, Low-Power D/A Converters

获取价格

DAC-1025SM DATEL 10-Bit, 250MSPS, Low-Power D/A Converters

获取价格

DAC102S085 TI DAC102S085 10-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail

获取价格

DAC102S085 NSC 10-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output

获取价格

DAC102S085_07 NSC 10-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output

获取价格

DAC102S085CIMM NSC 10-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output

获取价格