DAC-1025
10-Bit, 250MSPS, Low-Power D/A Converters
TECHNICAL NOTES
Theory of Operation
The full scale output current of the converter is a function of both the reference voltage and
the value of RSET. IOUT should be within the 2mA to 20mA range. Signal to noise as well as
SFDR performance may degrade slightly when operating with a low full scale output of 2mA.
If the internal reference is used, the voltage at GAINADJ (VGAINADJ), pin 18, will equal ap-
proximately 1.2Volts. If an external reference is used, the voltage at GAINADJ will equal the
external reference.
The DAC-1025 is a 10-Bit, 20mA currentoutput, CMOS, digital to analog converter with a
maximum conversion rate of250MSPS anda recommendedpower supply range of+3.0to
+3.6Volts .The design topology incorporates segmented current source circuitry with the
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remaining lower bits comprised ofbinary weighted current sources. In earlier D/A design
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major code transitions such as ¼, ½, and ¾ of the full scale range.The reduction of current
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spurious free dynamic range and signal to noise ratio.
IOUT Full Scale can be calculated as:
IOUT FS = (VGAINADJ/RSET) x 32
If the full scale output current is set to 20mA, by using the internal voltage reference (1.2V)
BOEꢀBꢀꢋꢊꢌꢋLƆꢀ3SET resistor, then the input tooutput transfer function will be according to the
following table.
Output Current
IOUTA and IOUTB of the DAC-1025 provide complementary output current.The sum of
IOUTA and IOUTB is always equal to the full scale output current minus one LSB. For single-
ended applications, a load resistor can be used to convert the output current to a voltage.
It is recommendedthat the unusedoutput be terminated with an equivalent value
resistance or connected to AGND.The voltage developed at the output must not exceed the
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produce the desired output voltage:
INPUT CODE / IOUT
INPUTCODE (B1 - B14)
1111111111
IOUTA (mA)
IOUTB (mA)
20
10
0
0
00 0000 0000
10
20
00 0000 0000
Digital Inputs / Propogation Delay
VOUT = IOUT x RLOAD
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terminated at the DGND ground plane should be used if driving the digital inputs from a
length of more than several inches.
The DAC requirestworising edge CLK commands to produce the analogoutput.The rising
edge of the Nth CLK signal stores the 10 bit inputword in the LVCMOS input registers.The
subsequent N+1 rising edge CLK command completes the conversion process bringing out the
Nth output for IOUTA and IOUTB.
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harmonic rejection.The SFDR measurements in this data sheet were attained using a 1:1
transformer on the output of the DAC (see Figure 2).With the center tapgrounded, the
output swing of pins 21 and 22 will be biased at zero volts. It is importantto note here that
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tion.The loading as shown in Figure 2 will result in a 500mV signal at the outputof the
transformer if the full scale output current of the DAC is set to 20mA.
Power Supplies
To maintain optimal SFDR and SNR performance it is recommended that separate supplies
ranging between +3.0V to +3.6V are used for AVDD and DVDD. The DAC-1025 is capable of
operating with supplies as low as +2.7V but the SFDR performance may be degraded. Reduc-
ing the full scale output current to 2mA could improve this parameter. To minimize power
supply noise, 0.1uF capacitors should be placed as close as possible to the converter’s power
supply pins, AVDD and DVDD. Be assured that capacitors are bypassed to their proper AGND or
DGND planes.
Vout = 2 x Iout x Requivalent.
Figure 2
Ground Planes
It is recommended that separate AGND and DGND ground planes be used.These two planes
should may be connected at the DAC, however, the optimal connection location of the two
planes may be system dependent. If separate DGND and AGND planes are used, all of the
digital components and switching signals should be located over the DGND and all critical
analog components andsignals located over the AGND plane. In addition, a signal ground can
be employed for all low currentsignal path grounding.
Voltage Reference
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ppm/°C over the operating temperature range. It is recommended that a bypass capacitor
be placed as close as possible to the REFI/O pin and bypassed to AGND. The REFSEL (pin 16)
selects whether an internal or external reference is used.. The internal reference can be
selected if pin 16 is tied to AGND. If an external reference is desired, then pin 16 should be
tied to AVDD, with the external reference beingdriven into REFI/O, pin 17.
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01 Feb 2016 MDA_DAC-1025.C01.D1 Page3 of 6
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