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CYW180-51SXT PDF预览

CYW180-51SXT

更新时间: 2024-02-04 08:26:38
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
10页 183K
描述
Peak Reducing EMI Solution

CYW180-51SXT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.38
Is Samacsys:N其他特性:ALSO OPERATES AT 5V SUPPLY
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.889 mm湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:28 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:28 MHz
认证状态:Not Qualified座面最大高度:1.727 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.8985 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CYW180-51SXT 数据手册

 浏览型号CYW180-51SXT的Datasheet PDF文件第1页浏览型号CYW180-51SXT的Datasheet PDF文件第2页浏览型号CYW180-51SXT的Datasheet PDF文件第4页浏览型号CYW180-51SXT的Datasheet PDF文件第5页浏览型号CYW180-51SXT的Datasheet PDF文件第6页浏览型号CYW180-51SXT的Datasheet PDF文件第7页 
W180  
input. The output frequency is then equal to the ratio of P/Q  
times the reference frequency. (Note: For the W180 the output  
frequency is equal to the input frequency.) The unique feature  
of the Spread Spectrum Frequency Timing Generator is that a  
modulating waveform is superimposed at the input to the VCO.  
This causes the VCO output to be slowly swept across a  
predetermined frequency band.  
Overview  
The W180 products are one series of devices in the Cypress  
PREMIS family. The PREMIS family incorporates the latest  
advances in PLL spread spectrum frequency synthesizer  
techniques. By frequency modulating the output with a  
low-frequency carrier, peak EMI is greatly reduced. Use of this  
technology allows systems to pass increasingly difficult EMI  
testing without resorting to costly shielding or redesign.  
Because the modulating frequency is typically 1000 times  
slower than the fundamental clock, the spread spectrum  
process has little impact on system performance.  
In a system, not only is EMI reduced in the various clock lines,  
but also in all signals which are synchronized to the clock.  
Therefore, the benefits of using this technology increase with  
the number of address and data lines in the system. The  
Simplified Block Diagram on page 1 shows a simple imple-  
mentation.  
Frequency Selection With SSFTG  
In Spread Spectrum Frequency Timing Generation, EMI  
reduction depends on the shape, modulation percentage, and  
frequency of the modulating waveform. While the shape and  
frequency of the modulating waveform are fixed for a given  
frequency, the modulation percentage may be varied.  
Functional Description  
Using frequency select bits (FS2:1 pins), the frequency range  
can be set (see Table 2). Spreading percentage is set with pin  
SS% as shown in Table 1.  
The W180 uses a phase-locked loop (PLL) to frequency  
modulate an input clock. The result is an output clock whose  
frequency is slowly swept over a narrow band near the input  
signal. The basic circuit topology is shown in Figure 1. The  
input reference signal is divided by Q and fed to the phase  
detector. A signal from the VCO is divided by P and fed back  
to the phase detector also. The PLL will force the frequency of  
the VCO output signal to change until the divided output signal  
and the divided reference signal match at the phase detector  
A larger spreading percentage improves EMI reduction.  
However, large spread percentages may either exceed  
system maximum frequency ratings or lower the average  
frequency to a point where performance is affected. For these  
reasons, spreading percentages options are provided.  
V
DD  
Clock Input  
CLKOUT  
Freq.  
Divider  
Q
Phase  
Detector  
Charge  
Pump  
Post  
Dividers  
Reference Input  
(EMI suppressed)  
Σ
VCO  
Modulating  
Waveform  
Feedback  
Divider  
P
PLL  
GND  
Figure 1. Functional Block Diagram  
Document #: 38-07156 Rev. *B  
Page 3 of 10  

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