CYRS1542AV18
CYRS1544AV18
72-Mbit QDR® II+ SRAM
Two-Word Burst Architecture
with RadStop™ Technology
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology
■ JTAG 1149.1 compatible test access port
■ DLL for accurate data placement
Radiation Performance
Radiation Data
Configurations
■ Total Dose =300 Krad
■ Soft error rate (both Heavy Ion and proton)
Heavy ions 1 × 10-10 upsets/bit-day with an external SECDED
EDAC Controller
CYRS1542AV18 – 4M × 18
CYRS1544AV18 – 2M × 36
■ Neutrons = 2.0 × 1014 N/cm2
Functional Description
■ Dose rate = 2.0 × 109 rad(Si)/sec
The CYRS1542AV18 and CYRS1544AV18 are synchronous
pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with
RadStop™ technology. Cypress’s state-of-the-art RadStop
Technology is radiation hardened through proprietary design and
process hardening techniques.
■ Dose rate survivability (rad(Si)/sec) = 1.5 × 10^11 rad(Si)/sec
■ Latch up immunity = 120 MeV.cm2/mg (125 °C)
Prototyping Options
The QDR II+ architecture consists of two separate ports to
access the memory: the read port and the write port. The read
port has dedicated data output bus to support read operations
and the write port has dedicated data input bus to support write
operations. QDR II+ architecture completely eliminates the need
to “turnaround” the data bus that exists with common I/O devices.
Each port is accessed through a common address bus.
Addresses for read are latched on the rising edges of the input
(K) clock whereas addresses for write are latched on the falling
edges of the input (K) clock. Accesses to the QDR II+ read and
write ports are completely independent of each another. To
maximize data throughput, both read and write ports are
equipped with DDR interfaces. Each address location is
associated with two 18-bit words for CYRS1542AV18, or two
36-bit words for CYRS1544AV18 that burst sequentially into or
out of the device. Since data can be transferred on every rising
edge of both input clocks (K and K#), memory bandwidth is
maximized while simplifying system design by eliminating bus
“turnarounds”.
■ Non qualified CYPT1542AV18 and CTPT1544AV18 devices
with same functional and timing characteristics in a 165-ball
Ceramic Column Grid Array (CCGA) package and Land Grid
Array (LGA) package without solder columns attached.
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 250-MHz clock for high bandwidth
■ Two-word burst on all accesses
■ Double data rate (DDR) interfaces on both read and write ports
at 250 MHz (data transferred at 500 MHz)
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ Single multiplexed address input bus latches address inputs
for both read and write ports
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks as well. Reads and
writes are conducted with on-chip synchronous self-timed
circuitry.
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
For a complete list of related resources, click here.
■ QDR® II operates with 2.0 cycle read latency when delay lock
loop (DLL) is enabled
■ Available in × 18 and × 36 configurations
Selection Guide
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
■ Available in 165-ball CCGA (21 × 25 ×2.83 mm)
■ HSTL inputs and variable drive HSTL output buffers
Description
250 MHz Unit
Maximum operating frequency
250
1700
1700
MHz
mA
Maximum operating current
(concurrent R/W)
× 18
× 36
Cypress Semiconductor Corporation
Document Number: 001-60006 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 27, 2019
5秒后页面跳转
NTC热敏电阻与PTC热敏电阻的应用原理及应用范围
GTO与普通晶闸管相比为什么可以自关断？为什么普通晶闸管不能呢？从GTO原理、应用范围带你了解原因及推荐型号
LF353数据手册解读：特性、应用、封装、引脚说明、电气参数及替换型号推荐
A4950资料手册解读：特性、应用、封装、引脚功能、电气参数及代换型号
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
