Datasheet > CYPAP112A3-10SXQT

CYPAP112A3-10SXQT

更新时间： 2023-09-03 20:34:40

品牌	Logo	应用领域
英飞凌 - INFINEON		光电二极管
页数	文件大小	规格书
17页	354K
描述
PG-DSO-10 tape and reel packing primary side startup controller with x-cap mode and pulse-transformer feedback for USB PD charger and adapters

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Primary side startup controller

Pinout

VDD700

OVP_AUX

AUX_IN

PULSEIN

GND

Figure 1

Table 1

Pin map

EZ-PD™ PAG1P pin description

Pin number Pin name

Description

Start-up power supply input. VDD700 is the power supply source during the

start-up phase. This pin can be connected to either the bridge rectifier output as

shown in Figure 2, or directly to the AC mains through a diode as shown in

Figure 3. This pin has a maximum voltage rating of 500 V.

VDD700

No connect

Timing resistor. The RT pin is used to connect to an external timing resistor of

499 k which determines the free running oscillator frequency FOSC. Oscillator

frequency is typically 30 kHz.

Pulse Edge Transformer (PET) input. Once the start-up phase is successfully

complete, EZ-PD™ PAG1P synchronizes to the secondary side pulses received at

the PULSEIN input. The secondary controller provides PWM control information to

the primary using a PET. The pulse amplitude shall not exceed V_PULSEINNEGAMP

and V_PULSEINPOSAMP and the pulse width shall be in the T_PULSEINPW range.

Soft-start pin. Connect a 0.1-µF capacitor to GND. The soft-start time is provided

in the specification section (Table 13). This pin also connects to the other end of

the pulse transformer. The external capacitor connected to the SS pin determines

the soft-start time. The duty cycle of the gate drive gradually increases to provide

a smooth transfer of power to the secondary side.

PULSEIN

GND

Ground

Primary side current sense input. Current sense input is used to monitor the

overcurrent fault scenario. Overcurrent fault is detected with the voltage between

this input and ground exceeds V_CSTH1 threshold.

Primary FET gate driver. EZ-PD™ PAG1P integrates a low side gate driver to drive

the gate of an external FET.

Datasheet

3 of 17

002-25572 Rev. *F

2022-05-18

1 234 5 6 7...17

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