Primary side startup controller
Functional description
3
Functional description
3.1
Soft-start
The Soft-start feature allows EZ-PD™ PAG1P to gradually increase the output voltage of the flyback converter till
the secondary side takes control of the regulation. Soft-start is used during initial start-up sequence and fault
condition. The duration of the soft-start is controlled by an external capacitor connected to the SS pin and the
frequency of the soft-start is determined by an external resistor connected to the RT pin. An internal current
source of 5 µA charges the external capacitor and the maximum amplitude for the soft-start ramp is 3.75 V. 3.75 V
dictates the maximum duty cycle. Under Soft-start, the maximum ON time of the primary FET is limited to 19 µs
which is equivalent to 70% duty cycle at 30 kHz. When the secondary side takes control, the maximum ON time
is limited to 25 µs.
3.2
X-cap mode
In EZ-PD™ PAG1P X-cap part, X-cap mode is detected when 3 V_VDD700UVRISE transitions occur within 64 ms. A
flag is set indicating the part is operating in X-cap mode. When 3 V_VDD700UVRISE transitions are not detected
within 64 ms after the flag is set, a line disconnect is detected and an internal discharge path is turned ON to
discharge the X-capacitor.
3.3
Secondary synchronization
During the start-up phase, if EZ-PD™ PAG1P sees appropriate input pulses at the PULSEIN pin, then it synchro-
nizes the primary FET control to the secondary pulses. The PWM control signal from the secondary side is coupled
to the primary side using a Pulse Edge Transformer (PET). The PET is an important component to ensure proper
frequency response and should have just an adequate Q-factor to avoid excessive overshoot. The positive pulse
from the PET is treated as primary FET turn-on signal and the negative pulse from the PET is treated as primary
FET turn-off signal. The pulse amplitude shall not exceed V_PULSEINNEGAMP and V_PULSEINPOSAMP and the
pulse width shall be within T_PULSEINPW range.
The synchronization path between the secondary and primary through the PET is also used for communication
of shutdown condition. Three consecutive negative pulses from the secondary side is treated as a shutdown
signal. On receiving such three consecutive negative pulses, EZ-PD™ PAG1P will shutdown after 200 ms.
3.4
Power circuit
EZ-PD™ PAG1P integrates a high voltage start-up regulator. During power-up, EZ-PD™ PAG1P shall be powered
from the line input via the VDD700 pin. Once voltage on the auxiliary winding is available from the secondary side,
EZ-PD™ PAG1P switches its power supply input to AUX_IN pin and no power will be sourced from the VDD700 pin.
3.5
Overcurrent and overvoltage fault protection
EZ-PD™ PAG1P implements overcurrent protection. When the CS pin voltage exceeds V_CSTH1, EZ-PD™ PAG1P
limits the primary current by turning OFF the primary FET.
EZ-PD™ PAG1P provides three types of voltage protection – protection against line undervoltage/overvoltage and
secondary overvoltage. The line undervoltage/overvoltage monitoring is via VDD700 pin and the respective
thresholds are V_VDDUVRISE and V_VDDOVRISE. Gate pulses are turned off until fault is removed. Once the
voltage on VDD700 is within operating range, EZ-PD™ PAG1P does an auto-restart.
In addition, EZ-PD™ PAG1P monitors the voltage on OVP_AUX pin for detecting overvoltage condition on the
secondary side. The voltage on the OVP_AUX pin is a scaled-down version of the secondary side voltage. When
voltage on OVP_AUX exceeds V_OVPAUXRISE, the gate driver is turned off. Once the voltage on OVP_AUX goes
below the fault range, EZ-PD™ PAG1P does an auto-restart. EZ-PD™ PAG1P monitors secondary overvoltage only
during start-up phase or during fault condition after auto-restart.
The flow chart in Figure 4 and the Functional block diagram show the operation of the chip.
Datasheet
7 of 17
002-25572 Rev. *F
2022-05-18
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