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CYIL1SM4000AA-GDCN

更新时间： 2024-01-10 05:50:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		传感器换能器图像传感器时钟
页数	文件大小	规格书
31页	1233K
描述
4 MegaPixel CMOS Image Sensor

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技术参数
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CYIL1SM4000AA-GDCN 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.26	其他特性：	ELECTRONIC SHUTTER
阵列类型：	FULL FRAME	主体宽度：	42 mm
主体高度：	3.25 mm	主体长度或直径：	42 mm
动态范围：	66 dB	帧速率：	15 fps
水平像素：	2048	外壳：	CERAMIC
主时钟：	33 MHz	安装特点：	SURFACE MOUNT
最大工作电流：	50 mA	最高工作温度：	60 °C
最低工作温度：		输出接口类型：	3-WIRE INTERFACE
输出范围：	-0.50-3.80V	输出类型：	DIGITAL VOLTAGE
封装形状/形式：	SQUARE	像素大小：	12X12 µm
灵敏度（V / lx.s）：	11.61 V/lx.s	传感器/换能器类型：	IMAGE SENSOR,CMOS
最大供电电压：	2.75 V	最小供电电压：	2.25 V
表面贴装：	YES	端接类型：	SOLDER
垂直像素：	2048	Base Number Matches：	1

CYIL1SM4000AA-GDCN 数据手册

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CYIL1SM4000AA

case the two output amplifiers are used to read out the imager.

The complete image sensor is designed for operation up to 66

MHz.

Sensor Architecture

A schematic drawing of the architecture is given in Figure 5. The

image core consists of a pixel array, one X-addressing and two

Y-addressing registers (only one drawn), pixel array drivers and

column amplifiers. The image sensor of 2048 x 2048 pixels is

read out in progressive scan. One or two output amplifiers read

out the image sensor. The output amplifiers are working at 66

MHz pixel rate nominal speed or each at 33 MHz pixel rate in

The structure allows having a programmable addressing in the

x-direction in steps of two and in the y-direction in steps of two

(only even start addresses in X-direction and Y-direction are

possible). The starting point of the address is uploadable by

means of the SPI

Figure 5. Block Diagram of Image Sensor

eos_y

On chip drivers

Reset, mem_hl,

precharge, sample

pixel array

2048 * 2048

Column ampliﬁers

X shift register

sync_y

Clk_y

eos_x

Clk_x

sync_x

2 differential

outputs

DAC

SPI

Logic blocks

The 6T Pixel

To obtain the global shutter feature combined with a high sensitivity and good Parasitic Light Sensitivity (PLS), the pixel architecture

given in Figure 6 is implemented.

Figure 6. 6T Pixel Architecture

Vpix

Vmem

Row-Select

Sample

Reset

This pixel architecture is designed in a 12 μm x 12 μm pixel pitch. The pixel is designed to meet the specifications described in Table 1

and Table 2.

Document Number: 38-05712 Rev. *C

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