CY8C95xx Preliminary Data Sheet
Overview
Multi-Port I/O Device
Device Access Addressing
This device allows the user to set various configurations and I/O
operations through internal registers.
Following a start condition, the I2C master device sends a byte
to address an I2C slave. This address selects the device to be
accessed in the CY8C95xx. By default there are two possible
address formats in binary representation: 010000A0X and
101000A0X. The first is used to access the multi-port device
and the second to access the EEPROM. If additional address
lines (A1-A6) are used then the Device Addressing Table 1-2
defines the device addresses. This addressing method uses a
technique called Extendable Soft Addressing™, described later
in this document.
Each data transfer is preceded by the command byte. This byte
is used as a pointer to a register that will receive or transmit
data. Available registers are listed in Table 3-1, “The Device
Register Address Map,” on page 11.
Table 1-2. Device Addressing
Multi-Port Device
EEPROM Device
01
0
0
0
0
0
0
0
0
0
0
0
A0 R/W
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
A0 R/W
1
1
1
1
A1 A0 R/W
A1 A0 R/W
0
A2 A1 A0 R/W
A2 A1 A0 R/W
0
A3 A2 A1 A0 R/W
A3 A2 A1 A0 R/W
0
A4 A3 A2 A1 A0 R/W
A4 A3 A2 A1 A0 R/W
0
A5 A4 A3 A2 A1 A0 R/W
A5 A4 A3 A2 A1 A0 R/W
A6 A5 A4 A3 A2 A1 A0 R/W A6 A5 A4 A3 A2 A1 A0 R/W
When all address lines A1-A6 are used, the device being
accessed is defined by the first byte following the address in the
write transaction. If the most significant bit (MSb) of this byte is
‘0’, this byte is treated as a command (register address) byte of
the multi-port device. If the MSb is ‘1’, this byte is the first of a 2-
byte EEPROM address. In this case, the device will mask the
MSb to determine the EEPROM address.
Serial EEPROM Device
EEPROM reading and writing operations require 2 bytes, AHI
and ALO, which indicate which memory address to use.
To read one or more bytes, the master device addresses the
unit with a write cycle (= 0) to send AHI followed by ALO, read-
dresses the unit with a read cycle (= 1), and reads one or more
data bytes. Each data byte read will increment the internal
address counter by one up to the end of the EEPROM address
space. A read or write beyond the end of the EEPROM address
space should result in a NAK response by the Port Expander.
To write data to the EEPROM, the master device performs one
write cycle, with the first two bytes being AHI followed by ALO.
This is followed by one or more data bytes. In the case of block
writing it is advisable to set the starting address on the begin-
ning of the 64-byte boundary, for example 01C0h or 0080h, but
this is not mandatory. When a 64-byte boundary is crossed in
the EEPROM, the I2C clock is stretched while the device per-
forms an EEPROM write sequence. If the end of available
EEPROM space is reached, then further writes will be
responded to with a NAK.
Refer to Figure 2-2, “Memory Reading and Writing,” on
page 10, which illustrates memory reading and writing proce-
dures for the EEPROM device.
August 17, 2005
Document No. 38-12036 Rev. *A
3
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