PSoC® 5LP: CY8C56LP Family
Datasheet
1. Architectural Overview
Introducing the CY8C56LP family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5LP platform. The CY8C56LP family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Digital Interconnect
System Wide
Resources
Digital System
I2C
Master/
Slave
Universal Digital Block Array(24 x UDB)
8- Bit
Timer
Quadrature Decoder
16- Bit PRS
CAN 2.0
4- 25 MHz
( Optional)
16- Bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
22 Ω
Xtal
Osc
USB
PHY
UDB
8- Bit
FS USB
2.0
UDB
UDB
UDB
I 2C Slave
UDB
4x
Timer
8- Bit SPI
Logic
Timer
Counter
PWM
12- Bit SPI
UDB
UDB
UDB
UDB
UDB
IMO
Logic
32.768 KHz
( Optional)
UDB
UDB
UART
12- Bit PWM
RTC
Timer
System Bus
Program &
Debug
Memory System
CPU System
WDT
and
Wake
Interrupt
Cortex M3CPU
EEPROM
SRAM
Program
Controller
Debug&
Trace
Cache
Controller
PHUB
DMA
FLASH
EMIF
Boundary
Scan
ILO
Clocking System
Analog System
Digital
Filter
Block
Power Management
System
LCD Direct
Drive
+
4 x
ADCs
2 x
Opamp
POR and
LVD
3 per
Opamp
-
SAR
ADC
4 x SC/CT Blocks
(TIA, PGA, Mixer etc)
Sleep
Power
+
-
Temperature
Sensor
4 x
CMP
1.8 V LDO
SMP
1 x
Del Sig
ADC
4x DAC
CapSense
0. 5 to5.5 V
( Optional)
Figure 1-1 illustrates the major components of the CY8C56LP
family. They are:
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals. In
addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C56LP family these blocks can include four 16-bit timer,
counter, and PWM blocks; I2C slave, master, and multi-master;
Full-Speed USB; and Full CAN 2.0.
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
Document Number: 001-84935 Rev. *C
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