PSoC® 4: PSoC 4100S
Family Datasheet
Programmable System-on-Chip (PSoC)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
The PSoC 4100S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S products will
be upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
Serial Communication
■ 48-MHz ARM Cortex-M0+ CPU
■ Up to 64 KB of flash with Read Accelerator
■ Up to 8 KB of SRAM
■ Three independent run-time reconfigurable Serial
Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
Timing and Pulse-Width Modulation
Programmable Analog
■ Five 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
■ Two opamps with reconfigurable high-drive external and
high-bandwidthinternaldriveandComparatormodesandADC
input buffering capability. Opamps can operate in Deep Sleep
low-power mode.
■ Center-aligned, Edge, and Pseudo-random modes
■ Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■ 12-bit 1-Msps SAR ADC with differential and single-ended
modes, and Channel Sequencer with signal averaging
Up to 36 Programmable GPIO Pins
■ Single-slope 10-bit ADC function provided by a capacitance
sensing block
■ 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and
35-ball WLCSP packages
■ Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■ Any GPIO pin can be CapSense, analog, or digital
■ Two low-power comparators that operate in Deep Sleep
low-power mode
■ Drive modes, strengths, and slew rates are programmable
PSoC Creator Design Environment
Programmable Digital
■ Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■ Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
Low-Power 1.71-V to 5.5-V Operation
■ Applications Programming Interface (API) component for all
■ Deep Sleep mode with operational analog and 2.5-A digital
fixed-function and programmable peripherals
system current
Industry-Standard Tool Compatibility
Capacitive Sensing
■ After schematic entry, development can be done with
■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class
ARM-based industry-standard development tools
signal-to-noise ratio (SNR) (>5:1) and water tolerance
■ Cypress-supplied software component makes capacitive
sensing design easy
■ Automatic hardware tuning (SmartSense™)
LCD Drive Capability
■ LCD segment drive capability on GPIOs
Cypress Semiconductor Corporation
Document Number: 002-00122 Rev. *I
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198 Champion Court
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San Jose, CA 95134-1709
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408-943-2600
Revised April 26, 2017