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CY8C4146LQI-S423 PDF预览

CY8C4146LQI-S423

更新时间: 2024-02-06 02:41:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟外围集成电路
页数 文件大小 规格书
41页 461K
描述
Multifunction Peripheral, CMOS, QFN-40

CY8C4146LQI-S423 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:compliantECCN代码:3A991.A.3
HTS代码:8542.31.00.01风险等级:5.79
地址总线宽度:边界扫描:NO
总线兼容性:I2C; SPI; UART最大时钟频率:48 MHz
外部数据总线宽度:JESD-30 代码:S-XQCC-N40
长度:6 mmI/O 线路数量:34
端子数量:40最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
RAM(字数):8000座面最大高度:0.6 mm
最大供电电压:5.5 V最小供电电压:1.71 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6 mmBase Number Matches:1

CY8C4146LQI-S423 数据手册

 浏览型号CY8C4146LQI-S423的Datasheet PDF文件第2页浏览型号CY8C4146LQI-S423的Datasheet PDF文件第3页浏览型号CY8C4146LQI-S423的Datasheet PDF文件第4页浏览型号CY8C4146LQI-S423的Datasheet PDF文件第5页浏览型号CY8C4146LQI-S423的Datasheet PDF文件第6页浏览型号CY8C4146LQI-S423的Datasheet PDF文件第7页 
PSoC® 4: PSoC 4100S  
Family Datasheet  
Programmable System-on-Chip (PSoC)  
General Description  
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an  
ARM® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.  
The PSoC 4100S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard  
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable  
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S products will  
be upward compatible with members of the PSoC 4 platform for new applications and design needs.  
Features  
32-bit MCU Subsystem  
Serial Communication  
48-MHz ARM Cortex-M0+ CPU  
Up to 64 KB of flash with Read Accelerator  
Up to 8 KB of SRAM  
Three independent run-time reconfigurable Serial  
Communication Blocks (SCBs) with re-configurable I2C, SPI,  
or UART functionality  
Timing and Pulse-Width Modulation  
Programmable Analog  
Five 16-bit timer/counter/pulse-width modulator (TCPWM)  
blocks  
Two opamps with reconfigurable high-drive external and  
high-bandwidthinternaldriveandComparatormodesandADC  
input buffering capability. Opamps can operate in Deep Sleep  
low-power mode.  
Center-aligned, Edge, and Pseudo-random modes  
Comparator-based triggering of Kill signals for motor drive and  
other high-reliability digital logic applications  
12-bit 1-Msps SAR ADC with differential and single-ended  
modes, and Channel Sequencer with signal averaging  
Up to 36 Programmable GPIO Pins  
Single-slope 10-bit ADC function provided by a capacitance  
sensing block  
48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and  
35-ball WLCSP packages  
Two current DACs (IDACs) for general-purpose or capacitive  
sensing applications on any pin  
Any GPIO pin can be CapSense, analog, or digital  
Two low-power comparators that operate in Deep Sleep  
low-power mode  
Drive modes, strengths, and slew rates are programmable  
PSoC Creator Design Environment  
Programmable Digital  
Integrated Development Environment (IDE) provides  
schematic design entry and build (with analog and digital  
automatic routing)  
Programmable logic blocks allowing Boolean operations to be  
performed on port inputs and outputs  
Low-Power 1.71-V to 5.5-V Operation  
Applications Programming Interface (API) component for all  
Deep Sleep mode with operational analog and 2.5-A digital  
fixed-function and programmable peripherals  
system current  
Industry-Standard Tool Compatibility  
Capacitive Sensing  
After schematic entry, development can be done with  
Cypress CapSense Sigma-Delta (CSD) provides best-in-class  
ARM-based industry-standard development tools  
signal-to-noise ratio (SNR) (>5:1) and water tolerance  
Cypress-supplied software component makes capacitive  
sensing design easy  
Automatic hardware tuning (SmartSense™)  
LCD Drive Capability  
LCD segment drive capability on GPIOs  
Cypress Semiconductor Corporation  
Document Number: 002-00122 Rev. *I  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 26, 2017  

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