PSoC™ Mixed-Signal Array
Final Data Sheet
CY8C21123,
CY8C21223, and CY8C21323
Features
■ Powerful Harvard Architecture Processor
■ M8C Processor Speeds to 24 MHz
■ Low Power at High Speed
■ Flexible On-Chip Memory
■ Precision, Programmable Clocking
■ Internal ±2.5% 24/48 MHz Oscillator
■ Internal Oscillator for Watchdog and Sleep
■ 4K Flash Program Storage 50,000 Erase/Write
Cycles
■ 256 Bytes SRAM Data Storage
■ In-System Serial Programming (ISSP™)
■ Partial Flash Updates
■ 2.4V to 5.25V Operating Voltage
■ Programmable Pin Configurations
■ 25 mA Drive on All GPIO
■ Operating Voltages Down to 1.0V Using
On-Chip Switch Mode Pump (SMP)
■ Industrial Temperature Range: -40°C to +85°C
■ Flexible Protection Modes
■ Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on All GPIO
■ EEPROM Emulation in Flash
■ Advanced Peripherals (PSoC Blocks)
■ 4 Analog Type “E” PSoC Blocks Provide:
- 2 Comparators with DAC Refs
■ Up to 8 Analog Inputs on GPIO
■ Configurable Interrupt on All GPIO
■ Complete Development Tools
■ Free Development Software
(PSoC™ Designer)
■ Additional System Resources
- Single or Dual 8-Bit 8:1 ADC
■ Full-Featured, In-Circuit Emulator and
■ I2C™ Master, Slave and Multi-Master to
■ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
Programmer
400 kHz
■ Full Speed Emulation
■ Watchdog and Sleep Timers
■ Complex Breakpoint Structure
■ 128 Bytes Trace Memory
- Full-Duplex UART, SPI™ Master or Slave
- Connectable to All GPIO Pins
■ User-Configurable Low Voltage Detection
■ Integrated Supervisory Circuit
■ Complex Peripherals by Combining Blocks
■ On-Chip Precision Voltage Reference
PSoC™ Functional Overview
Port 1 Port 0
PSoC
CORE
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Addi-
tionally, a fast CPU, Flash program memory, SRAM data mem-
ory, and configurable IO are included in a range of convenient
pinouts.
SystemBus
Global Digital Interconnect
Global Analog Interconnect
Flash
CPUCore
SROM
SRAM
Sleep and
Watchdog
Interrupt
Controller
(M8C)
Clock Sources
(Includes IMO and ILO)
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each PSoC device includes four digi-
tal blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 general purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
PSoC Block
Array
Analog
PSoC Block
Array
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (inter-
nal main oscillator) and ILO (internal low speed oscillator). The
Sw itch
Mode
Pump
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
Clocks
I2C
SYSTEM RESOURCES
February 25, 2005
© Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12022 Rev. *G
1
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