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CY8C21223-24PVXI PDF预览

CY8C21223-24PVXI

更新时间: 2024-02-16 06:06:09
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟微控制器光电二极管
页数 文件大小 规格书
33页 299K
描述
Multifunction Peripheral, CMOS, PDSO20, 0.210 INCH, LEAD FREE, SSOP-20

CY8C21223-24PVXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP, SSOP20,.3针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.75地址总线宽度:
位大小:8边界扫描:NO
CPU系列:M8C最大时钟频率:24.24 MHz
外部数据总线宽度:JESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:7.2 mm
湿度敏感等级:3I/O 线路数量:16
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/5 V
认证状态:Not QualifiedRAM(字节):256
RAM(字数):256ROM(单词):4096
ROM可编程性:FLASH座面最大高度:2 mm
速度:24 MHz子类别:Microcontrollers
最大压摆率:4 mA最大供电电压:5.25 V
最小供电电压:2.4 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:5.3 mmBase Number Matches:1

CY8C21223-24PVXI 数据手册

 浏览型号CY8C21223-24PVXI的Datasheet PDF文件第2页浏览型号CY8C21223-24PVXI的Datasheet PDF文件第3页浏览型号CY8C21223-24PVXI的Datasheet PDF文件第4页浏览型号CY8C21223-24PVXI的Datasheet PDF文件第5页浏览型号CY8C21223-24PVXI的Datasheet PDF文件第6页浏览型号CY8C21223-24PVXI的Datasheet PDF文件第7页 
PSoC™ Mixed-Signal Array  
Final Data Sheet  
CY8C21123,  
CY8C21223, and CY8C21323  
Features  
Powerful Harvard Architecture Processor  
M8C Processor Speeds to 24 MHz  
Low Power at High Speed  
Flexible On-Chip Memory  
Precision, Programmable Clocking  
Internal ±2.5% 24/48 MHz Oscillator  
Internal Oscillator for Watchdog and Sleep  
4K Flash Program Storage 50,000 Erase/Write  
Cycles  
256 Bytes SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
2.4V to 5.25V Operating Voltage  
Programmable Pin Configurations  
25 mA Drive on All GPIO  
Operating Voltages Down to 1.0V Using  
On-Chip Switch Mode Pump (SMP)  
Industrial Temperature Range: -40°C to +85°C  
Flexible Protection Modes  
Pull Up, Pull Down, High Z, Strong, or Open  
Drain Drive Modes on All GPIO  
EEPROM Emulation in Flash  
Advanced Peripherals (PSoC Blocks)  
4 Analog Type “E” PSoC Blocks Provide:  
- 2 Comparators with DAC Refs  
Up to 8 Analog Inputs on GPIO  
Configurable Interrupt on All GPIO  
Complete Development Tools  
Free Development Software  
(PSoC™ Designer)  
Additional System Resources  
- Single or Dual 8-Bit 8:1 ADC  
Full-Featured, In-Circuit Emulator and  
I2C™ Master, Slave and Multi-Master to  
4 Digital PSoC Blocks Provide:  
- 8- to 32-Bit Timers, Counters, and PWMs  
- CRC and PRS Modules  
Programmer  
400 kHz  
Full Speed Emulation  
Watchdog and Sleep Timers  
Complex Breakpoint Structure  
128 Bytes Trace Memory  
- Full-Duplex UART, SPIMaster or Slave  
- Connectable to All GPIO Pins  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
Complex Peripherals by Combining Blocks  
On-Chip Precision Voltage Reference  
PSoC™ Functional Overview  
Port 1 Port 0  
PSoC  
CORE  
The PSoC™ family consists of many Mixed-Signal Array with  
On-Chip Controller devices. These devices are designed to  
replace multiple traditional MCU-based system components  
with one, low cost single-chip programmable component. A  
PSoC device includes configurable blocks of analog and digital  
logic, as well as programmable interconnect. This architecture  
allows the user to create customized peripheral configurations,  
to match the requirements of each individual application. Addi-  
tionally, a fast CPU, Flash program memory, SRAM data mem-  
ory, and configurable IO are included in a range of convenient  
pinouts.  
SystemBus  
Global Digital Interconnect  
Global Analog Interconnect  
Flash  
CPUCore  
SROM  
SRAM  
Sleep and  
Watchdog  
Interrupt  
Controller  
(M8C)  
Clock Sources  
(Includes IMO and ILO)  
The PSoC architecture, as illustrated on the left, is comprised of  
four main areas: the Core, the System Resources, the Digital  
System, and the Analog System. Configurable global bus  
resources allow all the device resources to be combined into a  
complete custom system. Each PSoC device includes four digi-  
tal blocks. Depending on the PSoC package, up to two analog  
comparators and up to 16 general purpose IO (GPIO) are also  
included. The GPIO provide access to the global digital and  
analog interconnects.  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref.  
Digital  
PSoC Block  
Array  
Analog  
PSoC Block  
Array  
The PSoC Core  
The PSoC Core is a powerful engine that supports a rich  
instruction set. It encompasses SRAM for data storage, an  
interrupt controller, sleep and watchdog timers, and IMO (inter-  
nal main oscillator) and ILO (internal low speed oscillator). The  
Sw itch  
Mode  
Pump  
POR and LVD  
System Resets  
Internal  
Voltage  
Ref.  
Digital  
Clocks  
I2C  
SYSTEM RESOURCES  
February 25, 2005  
© Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12022 Rev. *G  
1

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