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CY8C20666A-24LQXIT PDF预览

CY8C20666A-24LQXIT

更新时间： 2024-01-04 10:23:17
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 控制器
页数 文件大小 规格书
51页 782K
描述
1.8 V Programmable CapSense® Controller with SmartSense™ Auto-tuning 1–33 Buttons, 0–6 Sliders

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CY8C20666A-24LQXIT 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：QFN包装说明：QFN-48
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.76Is Samacsys：N
地址总线宽度：位大小：8
边界扫描：NO总线兼容性：USB
CPU系列：M8C最大时钟频率：25.2 MHz
外部数据总线宽度：JESD-30 代码：S-XQCC-N48
JESD-609代码：e4长度：7 mm
湿度敏感等级：3I/O 线路数量：36
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC48,.27SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：1.8/5 V
认证状态：Not QualifiedRAM（字节）：2048
RAM（字数）：2000ROM（单词）：32768
ROM可编程性：FLASH座面最大高度：1 mm
速度：25.2 MHz子类别：Microcontrollers
最大压摆率：4 mA最大供电电压：5.5 V
最小供电电压：1.71 V标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：7 mmBase Number Matches：1

CY8C20666A-24LQXIT 数据手册

 浏览型号CY8C20666A-24LQXIT的Datasheet PDF文件第1页浏览型号CY8C20666A-24LQXIT的Datasheet PDF文件第2页浏览型号CY8C20666A-24LQXIT的Datasheet PDF文件第3页浏览型号CY8C20666A-24LQXIT的Datasheet PDF文件第5页浏览型号CY8C20666A-24LQXIT的Datasheet PDF文件第6页浏览型号CY8C20666A-24LQXIT的Datasheet PDF文件第7页 
CY8C20XX6A/S  
®
required tuning parameters. SmartSense allows engineers to go  
from prototyping to mass production without re-tuning for  
manufacturing variations in PCB and/or overlay material  
properties.  
PSoC Functional Overview  
The PSoC family consists of on-chip controller devices, which  
are designed to replace multiple traditional microcontroller unit  
(MCU)-based components with one, low cost single-chip  
SmartSense_EMC  
programmable component.  
A
PSoC device includes  
configurable analog and digital blocks, and programmable  
interconnect. This architecture allows the user to create  
customized peripheral configurations, to match the requirements  
of each individual application. Additionally, a fast CPU, Flash  
program memory, SRAM data memory, and configurable I/O are  
included in a range of convenient pinouts.  
In addition to the SmartSense auto tuning algorithm to remove  
manual tuning of CapSense applications, SmartSense_EMC  
user module incorporates a unique algorithm to improve  
robustness of capacitive sensing algorithm/circuit against high  
frequency conducted and radiated noise. Every electronic device  
must comply with specific limits for radiated and conducted  
external noise and these limits are specified by regulatory bodies  
(for example, FCC, CE, U/L and so on). A very good PCB layout  
design, power supply design and system design is a mandatory  
for a product to pass the conducted and radiated noise tests. An  
ideal PCB layout, power supply design or system design is not  
often possible because of cost and form factor limitations of the  
product. SmartSense_EMC with superior noise immunity is well  
suited and handy for such applications to pass radiated and  
conducted noise test.  
The architecture for this device family, as shown in the Logic  
Block Diagram on page 2, consists of three main areas:  
■ The Core  
■ CapSense Analog System  
■ System Resources (including a full-speed USB port).  
A common, versatile bus allows connection between I/O and the  
analog system.  
Figure 1. CapSense System Block Diagram  
Each CY8C20XX6A/S PSoC device includes a dedicated  
CapSense block that provides sensing and scanning control  
circuitry for capacitive sensing applications. Depending on the  
PSoC package, up to 36 GPIO are also included. The GPIO  
provides access to the MCU and analog mux.  
CS1  
IDAC  
CS2  
PSoC Core  
The PSoC Core is a powerful engine that supports a rich  
instruction set. It encompasses SRAM for data storage, an  
interrupt controller, sleep and watchdog timers, and IMO and  
ILO. The CPU core, called the M8C, is a powerful processor with  
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit  
Harvard-architecture microprocessor.  
CSN  
Vr  
Reference  
Buffer  
Cinternal  
CapSense System  
The analog system contains the capacitive sensing hardware.  
Several hardware algorithms are supported. This hardware  
performs capacitive sensing and scanning without requiring  
external components. The analog system is composed of the  
CapSense PSoC block and an internal 1 V or 1.2 V analog  
reference, which together support capacitive sensing of up to  
33 inputs . Capacitive sensing is configurable on each GPIO  
pin. Scanning of enabled CapSense pins are completed quickly  
and easily across multiple ports.  
Cexternal (P0[1]  
or P0[3])  
Comparator  
Mux  
Mux  
Refs  
[2]  
Cap Sense Counters  
CSCLK  
SmartSense  
SmartSense is an innovative solution from Cypress that removes  
manual tuning of CapSense applications. This solution is easy to  
use and provides a robust noise immunity. It is the only  
auto-tuning solution that establishes, monitors, and maintains all  
CapSense  
Clock Select  
IMO  
Oscillator  
Note  
2
2. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I C + 1 pin for modulator capacitor.  
Document Number: 001-54459 Rev. *T  
Page 4 of 51  
1234567...51

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