CY7C4425/4205/4215
CY7C4225/4235/4245
Selection Guide
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
100
8
66.7
10
15
4
40
15
25
6
28.6
20
35
7
10
3
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
0.5
8
1
1
2
10
45
50
15
45
50
20
45
50
Operating Current (I
(mA) @ freq=20MHz
)
Commercial
Industrial
45
50
CC2
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
Density
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
Packages
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
Pin Definitions
Signal Name
Description
I/O
Function
D
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I
O
I
Data inputs for an 18-bit bus
Data outputs for an 18-bit bus
Enables the WCLK input
Enables the RCLK input
0–17
Q
0–17
WEN
REN
I
WCLK
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
FF
PAE
Programmable
Almost Empty
value programmed into the FIFO. PAE is asynchronous when V /SMODE is tied
CC
to V ; it is synchronized to RCLK when V /SMODE is tied to V .
CC
CC
SS
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V /SMODE is tied to
CC
V
; it is synchronized to WCLK when V /SMODE is tied to V
.
CC
CC
SS
LD
Load
I
I
When LD is LOW, D
ble-flag-offset register.
(O
) are written (read) into (from) the programma-
0 - 17
0 - 17
FL/RT
First Load/
Retransmit
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to V ; all other
SS
devices will have FL tied to V . In standard mode of width expansion, FL is tied
CC
to V on all devices.
SS
Not Cascaded - Tied to V . Retransmit function is also available in standalone
SS
mode by strobing RT.
WXI
Write Expansion
Input
I
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to V
.
SS
3