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CY7C408A-15LMBR

更新时间： 2024-02-02 14:48:50
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
16页 347K
描述
FIFO, 64X8, 40ns, Asynchronous, CMOS, CQCC28, CERAMIC, LCC-28

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中文翻译

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CY7C408A-15LMBR 技术参数

生命周期：Obsolete零件包装代码：SOJ
包装说明：SOJ,针数：28
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.82
最长访问时间：40 ns其他特性：FALL THRU 65NS; BUBBLE BACK 65NS
周期时间：66.67 nsJESD-30 代码：R-PDSO-J28
长度：17.907 mm内存密度：512 bit
内存宽度：8功能数量：1
端子数量：28字数：64 words
字数代码：64工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64X8输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：SOJ封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：3.556 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：DUAL宽度：7.5057 mm
Base Number Matches：1

CY7C408A-15LMBR 数据手册

 浏览型号CY7C408A-15LMBR的Datasheet PDF文件第6页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第7页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第8页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第10页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第11页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第12页 
CY7C408A  
CY7C409A  
Possible Minimum Pulse Width Violation at the Boundary  
Conditions  
3). Two things should be noted when this configuration is im-  
plemented.  
If the handshaking signals IR and OR are not properly used to  
generate the SI and SO signals, it is possible to violate the  
minimum (effective) SI and SO positive pulse widths at the full  
and empty boundaries.  
Secondly, the frequency at the cascade interface is less than  
the 35 MHz rate at which the external clocks may operate.  
Therefore, the first device has its data shifted in faster than it  
is shifted out, and eventually this device becomes momentarily  
full. When this occurs, the maximum sustainable external  
clock frequency changes from 35 MHz to the cascade inter-  
Cascading the 7C408/9A-35 Above 25 MHz  
[28]  
face frequency.  
First, the capacity of N cascaded FIFOs is decreased from N  
× 64 to (N × 63) + 1.  
[29]  
When data packets  
are transmitted, this phenomenon does  
not occur unless more than three FIFOs are depth cascaded.  
For example, if two FIFOs are cascaded, a packet of 127 (=2  
× 63 + 1) words may be shifted in at up to 35 MHz and then  
the entire packet may be shifted out at up to 35 MHz.  
If cascaded FIFOs are to be operated with an external clock  
rate greater than 25 MHz, the interface IR signal must be in-  
verted before being fed back to the interface SO pin (Figure  
FULL  
EMPTY  
64  
63  
56  
55  
54  
32  
31  
30  
9
8
7
1
SHIFTOUT  
HF  
C408A–18  
AFE  
Figure 2. Shifting Words Out.  
A
1
B
C
N
IR  
SI  
IR  
SI  
SO  
OR  
IR  
SI  
SO  
OR  
IR  
SI  
SO  
OR  
IR  
SO  
X
X
SI  
X
OR  
X
D
IN  
D
INX  
D
OUTX  
2
UPSTREAM  
C408A–19  
DOWNSTREAM  
Figure 3. Cascaded Configuration Above 25 MHz.  
128x 9 Configuration  
HF/AFE  
HF/AFE  
SHIFT IN  
SI  
IR  
OR  
SO  
SI  
IR  
OR  
SO  
OUTPUT READY  
SHIFT OUT  
INPUT READY  
DI  
0
DO  
DI  
0
DO  
0
0
DI  
1
DO  
DI  
1
DO  
1
1
DO  
DO  
2
DI  
2
DI  
2
2
DI  
3
DO  
DI  
3
DO  
3
3
DI  
4
DO  
DI  
4
DO  
4
DATA OUT  
DATA IN  
4
DI  
5
DO  
DI  
5
DO  
5
5
DO  
DO  
6
DI  
6
DI  
6
6
DI  
7
DO  
DI  
7
DO  
7
7
DI  
DO  
DI  
DO  
8
8
8
8
MR  
MR  
C408A–20  
MR  
[22,23,24,25,26]  
Figure 4. Cascaded Configuration at or below 25 MHz  
.
9
1...6789101112...16

中文翻译

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CY7C408A-15VC CYPRESS

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CY7C408A-25DMB CYPRESS

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CY7C408A-25KMB CYPRESS

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 		x8 Asynchronous FIFO
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CY7C408A-25LMBR CYPRESS

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