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CY7C408A-15LMBR

更新时间： 2024-01-03 01:13:48
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
16页 347K
描述
FIFO, 64X8, 40ns, Asynchronous, CMOS, CQCC28, CERAMIC, LCC-28

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中文翻译

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CY7C408A-15LMBR 技术参数

生命周期：Obsolete零件包装代码：SOJ
包装说明：SOJ,针数：28
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.82
最长访问时间：40 ns其他特性：FALL THRU 65NS; BUBBLE BACK 65NS
周期时间：66.67 nsJESD-30 代码：R-PDSO-J28
长度：17.907 mm内存密度：512 bit
内存宽度：8功能数量：1
端子数量：28字数：64 words
字数代码：64工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64X8输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：SOJ封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：3.556 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：DUAL宽度：7.5057 mm
Base Number Matches：1

CY7C408A-15LMBR 数据手册

 浏览型号CY7C408A-15LMBR的Datasheet PDF文件第7页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第8页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第9页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第11页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第12页浏览型号CY7C408A-15LMBR的Datasheet PDF文件第13页 
CY7C408A  
CY7C409A  
192x 27Configuration  
HF/AFE  
HF/AFE  
SHIFTOUT  
IR  
SI  
SO  
OR  
IR  
SI  
SO  
OR  
IR  
SI  
SO  
OR  
DI  
0
DO  
DI  
0
DO  
DI  
0
DO  
0
0
0
DI  
1
DO  
DI  
1
DO  
DI  
1
DO  
1
1
1
DI  
2
DO  
DI  
2
DO  
DI  
2
DO  
2
2
2
DI  
3
DO  
DI  
3
DO  
DI  
3
DO  
3
3
3
DI  
4
DO  
DI  
4
DO  
DI  
4
DO  
4
4
4
DI  
5
DO  
DI  
5
DO  
DI  
5
DO  
5
5
5
DI  
6
DO  
DI  
6
DO  
DI  
6
DO  
6
6
6
DI  
7
DO  
DI  
7
DO  
DI  
7
DO  
7
7
7
DI  
DO  
DI  
DO  
DI  
DO  
8
8
8
8
8
8
MR  
MR  
MR  
MR  
MR  
MR  
MR  
MR  
MR  
COMPOSITE  
INPUT READY  
COMPOSITE  
OUTPUT READY  
IR  
SI  
SO  
OR  
IR  
SI  
SO  
OR  
IR  
SI  
SO  
OR  
DI  
DO  
DI  
DO  
DI  
DO  
0
0
0
0
0
0
DI  
DO  
DI  
DO  
DI  
DO  
1
1
1
1
1
1
DI  
DO  
DI  
DO  
DI  
DO  
2
2
2
2
2
2
DI  
DO  
DI  
DO  
DI  
DO  
3
3
3
3
3
3
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DO  
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DO  
DI  
DO  
4
4
4
4
4
4
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DI  
DO  
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DO  
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5
5
5
5
5
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DO  
6
6
6
6
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6
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DO  
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DO  
DI  
DO  
7
7
7
7
7
7
DI  
8
DO  
DI  
8
DO  
DI  
8
DO  
8
8
8
SHIFTIN  
IR  
SI  
SO  
OR  
IR  
SI  
SO  
OR  
IR  
SI  
SO  
OR  
DI  
DO  
DI  
DO  
DI  
DO  
0
0
0
0
0
0
DI  
DO  
DI  
DO  
DI  
DO  
1
1
1
1
1
1
DI  
DO  
DI  
DO  
DI  
DO  
2
2
2
2
2
2
DI  
DO  
DI  
DO  
DI  
DO  
3
3
3
3
3
3
DI  
DO  
DI  
DO  
DI  
DO  
4
4
4
4
4
4
DI  
DO  
DI  
DO  
DI  
DO  
5
5
5
5
5
5
DI  
DO  
DI  
DO  
DI  
DO  
6
6
6
6
6
6
DI  
DO  
DI  
DO  
DI  
DO  
7
7
7
7
7
7
DI  
8
DO  
DI  
8
DO  
DI  
8
DO  
8
8
8
MR  
C408A–21  
[23,24,25,26,27]  
Figure 5. Depth and Width Expansion  
.
Notes:  
22. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the  
devices.  
23. When the memory is empty the last word read will remain on the outputs until the master reset is strobed or a new data word falls through to the output.  
24. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until  
the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.  
25. If SO is held HIGH while the memory is empty and a word is written into the input, that word will fall through the memory to the output. OR will go HIGH for  
one internal cycle (at least tPOR) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will  
line up behind the first word and will not appear on the outputs until SO has been brought LOW.  
26. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH, and OR goes LOW.  
27. FIFOs are expandable in depth and width. However, in forming wider words, two external gates are required to generate composite input ready and output  
ready flags. This need is due to the variation of delays of the FIFOs  
28. Because the data throughput in the cascade interface is dependent on the inverter delay, it is recommended that the fastest available inverter be used.  
29. Transmission of data packets assumes that up to the maximum cumulative capacity of the FIFOs is shifted in without simultaneous shift out clock occurring.  
The complement of this holds when data is shifted out as a packet.  
10  
1...78910111213...16

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CY7C408A-15VC CYPRESS

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CY7C408A-15VCT CYPRESS

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CY7C408A-25DMB CYPRESS

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CY7C408A-25KMB CYPRESS

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CY7C408A-25LMB CYPRESS

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CY7C408A-25LMBR CYPRESS

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