CY7C1613KV18/CY7C1615KV18
144-Mbit QDR® II SRAM Four-Word
Burst Architecture
144-Mbit QDR® II SRAM Four-Word Burst Architecture
Features
Configuration
■ Separate independent read and write data ports
❐ Supports concurrent transactions
CY7C1613KV18 – 8 M × 18
CY7C1615KV18 – 4 M × 36
■ 333 MHz clock for high bandwidth
Functional Description
■ Four-word burst for reducing address bus frequency
The CY7C1613KV18, and CY7C1615KV18 are 1.8-V
■ DoubleDataRate(DDR)interfacesonbothreadandwriteports
(data transferred at 666 MHz) at 333 MHz
synchronous pipelined SRAMs, equipped with QDR® II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn around”
the data bus that exists with common I/O devices. Each port can
be accessed through a common address bus. Addresses for
read and write addresses are latched on alternate rising edges
of the input (K) clock. Accesses to the QDR II read and write
ports are completely independent of one another. To maximize
data throughput, both read and write ports are equipped with
DDR interfaces. Each address location is associated with four
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
18-bit
words
(CY7C1613KV18),
or
36-bit
words
(CY7C1615KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turnarounds”.
■ Quad data rate (QDR®) II operates with 1.5-cycle read latency
when DOFF is asserted high
■ Operates similar to a QDR I device with one-cycle read latency
when DOFF is asserted low
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ Available in × 18, and × 36 configurations
■ Full data coherency, providing most current data
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply
■ Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 ×17 ×1.4 mm)
For a complete list of related documentation, click here.
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive high-speed transceiver logic (HSTL) output
buffers
■ JTAG 1149.1 compatible test access port (TAP)
■ Phase Locked Loop (PLL) for accurate data placement
Selection Guide
Description
Maximum operating frequency
333 MHz
333
300 MHz
300
250 MHz Unit
250 MHz
Maximum operating current
× 18
× 36
760
710
Not Offered mA
830
1010
950
Cypress Semiconductor Corporation
Document Number: 001-44273 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 2, 2018
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