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CY7C145V-25JI PDF预览

CY7C145V-25JI

更新时间: 2024-02-21 21:13:46
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
21页 359K
描述
Dual-Port SRAM, 8KX9, 25ns, CMOS, PQCC68, PLASTIC, LCC-68

CY7C145V-25JI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:PLASTIC, LCC-68
针数:68Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.92最长访问时间:25 ns
I/O 类型:COMMONJESD-30 代码:S-PQCC-J68
JESD-609代码:e0长度:24.2316 mm
内存密度:73728 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9功能数量:1
端口数量:2端子数量:68
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX9
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:5.08 mm
最大待机电流:0.00005 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.185 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:24.2316 mm
Base Number Matches:1

CY7C145V-25JI 数据手册

 浏览型号CY7C145V-25JI的Datasheet PDF文件第2页浏览型号CY7C145V-25JI的Datasheet PDF文件第3页浏览型号CY7C145V-25JI的Datasheet PDF文件第4页浏览型号CY7C145V-25JI的Datasheet PDF文件第5页浏览型号CY7C145V-25JI的Datasheet PDF文件第6页浏览型号CY7C145V-25JI的Datasheet PDF文件第7页 
51  
CY7C138V/144V/006V/007V  
CY7C139V/145V/016V/017V  
PRELIMINARY  
3.3V 4K/8K/16K/32K x 8/9  
Dual-Port Static RAM  
• Automatic power-down  
Features  
• Expandable databusto16/18bitsormoreusingMaster/  
Slave chip select when using more than one device  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Pin select for Master or Slave  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
• 4K/8K/16K/32K x 8 organizations  
(CY7C0138V/144V/006V/007V)  
• 4K/8K/16K/32K x 9 organizations  
(CY7C0139V/145V/016V/017V)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 15/25 ns  
• Low operating power  
• Commercial and Industrial Temperature Ranges  
• Available in 80-pin TQFP (7C145V, 7C007V, 7C016V &  
7C017V), 64-pin TQFP (7C006V & 7C144V) and 68-pin  
PLCC (all except 7C017)  
Active: I = 115 mA (typical)  
CC  
• Pin-compatible and functionally equivalent to  
IDT70V05, 70V06, and 70V07.  
— Standby: I  
= 10 A (typical)  
µ
SB3  
• Fully asynchronous operation  
Logic Block Diagram  
R/W  
R/W  
CE  
L
R
R
R
CE  
L
OE  
OE  
L
[1]  
[1]  
8/9  
8/9  
I/O –I/O  
I/O –I/O  
0L  
7/8L  
0R  
7/8R  
I/O  
I/O  
Control  
Control  
[2]  
12–15  
12–15  
[2]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A
A
–A  
A
A
–A  
–A  
0L  
11–14L  
0R  
11–14R  
RAM Array  
12–15  
12–15  
[2]  
[2]  
–A  
0L  
11–14L  
0R  
11–14R  
CE  
CE  
Interrupt  
Semaphore  
Arbitration  
L
R
OE  
OE  
L
R
R/W  
R/W  
L
R
R
SEM  
SEM  
L
[3]  
L
[3]  
BUSY  
INT  
BUSY  
INT  
R
R
L
M/S  
Notes:  
1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.  
2. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices;  
3. BUSY is an output in master mode and an input in slave mode.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
November 4, 1997 - Revised February 24, 1998  

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