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CY7C1460AV25-225AC PDF预览

CY7C1460AV25-225AC

更新时间： 2024-11-08 07:56:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
27页 382K
描述
ZBT SRAM, 1MX36, CMOS, PQFP100,

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中文翻译

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CY7C1460AV25-225AC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：TQFP-100
Reach Compliance Code：compliant风险等级：5.82
最大时钟频率 (fCLK)：225 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：37748736 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：100
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.8/2.5,2.5 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.1 A
最小待机电流：2.38 V子类别：SRAMs
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm

CY7C1460AV25-225AC 数据手册

 浏览型号CY7C1460AV25-225AC的Datasheet PDF文件第2页浏览型号CY7C1460AV25-225AC的Datasheet PDF文件第3页浏览型号CY7C1460AV25-225AC的Datasheet PDF文件第4页浏览型号CY7C1460AV25-225AC的Datasheet PDF文件第5页浏览型号CY7C1460AV25-225AC的Datasheet PDF文件第6页浏览型号CY7C1460AV25-225AC的Datasheet PDF文件第7页 
CY7C1460AV25  
CY7C1462AV25  
CY7C1464AV25  
PRELIMINARY  
36-Mbit(1Mx36/2Mx18/512Kx72)PipelinedSRAM  
with NoBL™ Architecture  
Features  
Functional Description  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
— Available speed grades are 250, 200 and 167MHz  
• Internally self-timed output buffer control to eliminate  
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are  
2.5V, 1M x 36 / 2M x 18 /Synchronous pipelined burst SRAMs  
with No Bus Latency™ (NoBL™) logic, respectively. They are  
designed to support unlimited true back-to-back Read/Write  
operations with no wait states. The CY7C1460AV25/  
CY7C1462AV25/CY7C1464AV25 are equipped with the  
advanced (NoBL) logic required to enable consecutive  
Read/Write operations with data being transferred on every  
clock cycle. This feature dramatically improves the throughput  
of data in systems that require frequent Write/Read transitions.  
The CY7C1460AV25/ CY7C1462AV25/ CY7C1464AV25 are  
pin compatible and functionally equivalent to ZBT devices.  
the need to use asynchronous  
OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• Single 2.5V power supply  
• 2.5V/1.8V I/O operation  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle. Write operations are controlled by the  
Byte Write Selects (BWa–BWh for CY7C1464AV25,  
BWa–BWd for CY7C1460AV25 and BWa–BWb for  
CY7C1462AV25) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.4 ns (for 167-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• CY7C1460AV25 and CY7C1462AV25 available in 100  
TQFPand165fBGApackagesCY7C1464AV25available  
in 209-Ball fBGA package  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
• IEEE 1149.1 JTAG Boundary Scan  
• Burst capability—linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Logic Block Diagram-CY7C1460AV25 (1M x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05354 Rev. **  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised August 12, 2004  
1234567...27

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CY7C1460AV25-250BZC CYPRESS

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CY7C1460AV25-250BZXI CYPRESS

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