Datasheet > CY7C1380A-150AC

CY7C1380A-150AC

更新时间： 2025-09-10 07:18:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
32页	400K
描述
Cache SRAM, 512KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1380A-150AC 数据手册

CY7C1380A

CY7C1382A

PRELIMINARY

512K x 36 / 1M x 18 Pipelined SRAM

inputs, address-pipelining Chip Enable (CE), burst control in-

puts (ADSC, ADSP, and ADV), write enables (BWa, BWb,

BWc, BWd and BWE), and Global Write (GW).

Features

• Fast clock speed: 167, 150, 133, 100 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast OE access times: 3.4, 3.8, 4.2 and 5.0 ns

• Optimal for depth expansion

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data (DQ

) and the data

a,b,c,d

parity (DQP

nous.

) outputs, enabled by OE, are also asynchro-

a,b,c,d

• 3.3V (–5% / +10%) power supply

and DQP

apply to CY7C1380 and DQ and

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip enable for address pipeline

a,b,c,d

a,b,c,d a,b

DQP apply to CY7C1382. a, b, c, d each are 8 bits wide in

the case of DQ and 1 bit wide in the case of DP.

a,b

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• High-density, high-speed packages

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

Functional Description

controls DQa and DQPa. BWb controls DQ and DQP . BWc

controls DQcand DQPd. BWd controls DQd-DQd and DQPd.

BWa, BWb, BWc, and BWd can be active only with BWE being

LOW. GW being LOW causes all bytes to be written. WRITE

pass-through capability allows written data available at the out-

put for the immediately next READ cycle. This device also in-

corporates pipelined enable circuit for easy depth expansion

without penalizing system performance.

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1380A and CY7C1382A SRAMs integrate

524,288x36 and 1,048,576x18 SRAM cells with advanced

synchronous peripheral circuitry and a 2-bit counter for inter-

nal burst operation. All synchronous inputs are gated by reg-

isters controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

All inputs and outputs of the CY7C1380A and the CY7C1382A

are JEDEC standard JESD8-5 compatible.

Selection Guide

167 MHz

150 MHz

3.8

133 MHz

4.2

100 MHz

5.0

Maximum Access Time (ns)

3.4

350

Maximum Operating Current (mA)

Commercial

310

280

250

Maximum CMOS Standby Current (mA)

Shaded areas contain advance information.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

May 18, 2000

12 3 4 5 6 7...32

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与CY7C1380A-150AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1380A-167AC	CYPRESS	获取价格	Cache SRAM, 512KX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1380A-167BGC	CYPRESS	获取价格	Cache SRAM, 512KX36, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1380AV25-100BGC	CYPRESS	获取价格	Cache SRAM, 512KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1380AV25-133AC	CYPRESS	获取价格	Cache SRAM, 512KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1380AV25-150AC	CYPRESS	获取价格	Cache SRAM, 512KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1380AV25-150BGC	CYPRESS	获取价格	Cache SRAM, 512KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1380AV25-167AC	CYPRESS	获取价格	Cache SRAM, 512KX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1380B	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM
CY7C1380B-133AC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM
CY7C1380B-133AI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM

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