Datasheet > CY7C1041B-17VC

CY7C1041B-17VC

更新时间： 2024-02-19 13:57:20

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		内存集成电路静态存储器光电二极管
页数	文件大小	规格书
10页	344K
描述
256K x 16 Static RAM

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1041B-17VC 数据手册

CY7C1041B

Switching Characteristics^[4]Over the Operating Range

7C1041B-12

7C1041B-15

7C1041B-17

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

t_power

t_RC

V_CC(typical) to the First Access^[5]

Read Cycle Time

t_AA

Address to Data Valid

Data Hold from Address Change

CE LOW to Data Valid

OE LOW to Data Valid

OE LOW to Low Z

OE HIGH to High Z^{[6, 7]}

CE LOW to Low Z^[7]

CE HIGH to High Z^{[6, 7]}

CE LOW to Power-Up

CE HIGH to Power-Down

Byte Enable to Data Valid

Byte Enable to Low Z

Byte Disable to High Z

t_OHA

t_ACE

t_DOE

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_PU

t_PD

t_DBE

t_LZBE

t_HZBE

WRITE CYCLE^{[8, 9]}

t_WC

t_SCE

t_AW

Write Cycle Time

CE LOW to Write End

Address Set-Up to Write End

Address Hold from Write End

Address Set-Up to Write Start

WE Pulse Width

t_HA

t_SA

t_PWE

t_SD

Data Set-Up to Write End

Data Hold from Write End

WE HIGH to Low Z^[7]

t_HD

t_LZWE

t_HZWE

WE LOW to High Z^{[6, 7]}

t_BW

Byte Enable to End of Write

Notes:

4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

I_OL/I_OHand 30-pF load capacitance.

5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t_powertime has to be provided initially before a read/write operation

is started.

6. t_HZOE, t_HZCE, and t_HZWEare specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

7. At any given temperature and voltage condition, t_HZCEis less than t_LZCE, t_HZOEis less than t_LZOE, and t_HZWEis less than t_LZWEfor any given device.

8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of

these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t_HZWEand t_SD

1 2 345 6 7...10

下载PDF

与CY7C1041B-17VC相关器件

型号	品牌	描述	获取价格	数据表
CY7C1041B-17VCT	ROCHESTER	Standard SRAM, 256KX16, 17ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44	获取价格
CY7C1041B-17VI	CYPRESS	256K x 16 Static RAM	获取价格
CY7C1041B-17VIT	ROCHESTER	Standard SRAM, 256KX16, 17ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44	获取价格
CY7C1041B-17ZC	CYPRESS	256K x 16 Static RAM	获取价格
CY7C1041B-17ZC	ROCHESTER	暂无描述	获取价格
CY7C1041B-17ZI	CYPRESS	256K x 16 Static RAM	获取价格