Datasheet > CY7B991.5JIT

CY7B991.5JIT

更新时间： 2022-12-28 02:41:09

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
19页	514K
描述
Programmable Skew Clock Buffer

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CY7B991.5JIT 数据手册

CY7B991

CY7B992

Figure 1 shows the typical outputs with FB connected to a zero skew output.^[4]

Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

FBInput

REFInput

1Fx

2Fx

3Fx

4Fx

(N/A)

– 6t

– 4t

– 3t

(N/A)

– 2t

– 1t

(N/A)

+1t

+2t

+3t

(N/A)

+4t

+6t

(N/A)

LL/HH

DIVIDED

INVERT

Test Mode

The TEST input is a three level input. In normal system

operation, this pin is connected to ground, enabling the

CY7B991 or CY7B992 to operate as explained in “Skew Select

Matrix” on page 3. For testing purposes, any of the three level

inputs can have a removable jumper to ground, or be tied LOW

through a 100Ω resistor. This enables an external tester to

change the state of these pins.

If the TEST input is forced to its MID or HIGH state, the device

operates with its internal phase locked loop disconnected, and

input levels supplied to REF directly controls all outputs. Relative

output to output functions are the same as in normal mode.

In contrast with normal operation (TEST tied LOW), all outputs

function based only on the connection of their own function

selects inputs (xF0 and xF1) and the waveform characteristics of

the REF input.

Note

4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).

Document Number: 38-07138 Rev. *B

Page 4 of 19

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