Datasheet > CY62256V-55ZC

CY62256V-55ZC

更新时间： 2024-01-31 21:57:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	389K
描述
32K x 8 Static RAM

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中文翻译

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CY62256V-55ZC 数据手册

CY62256V

256K (32K x 8) Static RAM

Features

Functional Description^[1]

• Temperature Ranges

—Commercial: 0°C to 70°C

— Industrial: –40°C to 85°C

— Automotive: –40°C to 125°C

• Speed: 70 ns and 100 ns

• Low voltage range:

The CY62256V family is composed of two high-performance

CMOS static RAM’s organized as 32K words by 8 bits. Easy

memory expansion is provided by an active LOW chip enable

(CE) and active LOW output enable (OE) and three-state

drivers. These devices have an automatic power-down

feature, reducing the power consumption by over 99% when

deselected.

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/output pins

(I/O₀through I/O₇) is written into the memory location

addressed by the address present on the address pins (A₀

through A₁₄). Reading the device is accomplished by selecting

the device and enabling the outputs, CE and OE active LOW,

while WE remains inactive or HIGH. Under these conditions,

the contents of the location addressed by the information on

address pins are present on the eight data input/output pins.

— CY62256V (2.7V–3.6V)

— CY62256V25 (2.3V–2.7V)

• Low active power and standby power

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Package available in a standard 450-mil-wide (300-mil

body width) 28-lead narrow SOIC, 28-lead TSOP-1, and

reverse 28-lead TSOP-1 package

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable

(WE) is HIGH.

Logic Block Diagram

I/O

INPUTBUFFER

512 × 512

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05057 Rev. *D

Revised June 28, 2004

12 3 4 5 6 7...13

中文翻译

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与CY62256V-55ZC相关器件

型号	品牌	获取价格	描述	数据表
CY62256V-70RZC	CYPRESS	获取价格	32K x 8 Static RAM
CY62256V-70SNC	CYPRESS	获取价格	32K x 8 Static RAM
CY62256V-70SNCT	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, SOIC-28
CY62256V-70ZC	CYPRESS	获取价格	32K x 8 Static RAM
CY62256V-70ZCT	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, TSOP-28
CY62256V-70ZRI	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, REVERSE, TSOP1-28
CY62256V-70ZRIT	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, REVERSE, TSOP1-28
CY62256VL-55RZC	CYPRESS	获取价格	32K x 8 Static RAM
CY62256VL-55SNC	CYPRESS	获取价格	32K x 8 Static RAM
CY62256VL-55ZC	CYPRESS	获取价格	32K x 8 Static RAM

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