Datasheet > CY62128DV30

CY62128DV30

更新时间： 2024-02-23 17:24:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	198K
描述
1 Mb (128K x 8) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62128DV30 数据手册

CY62128DV30

MoBL^

1 Mb (128K x 8) Static RAM

power consumption by 90% when addresses are not toggling.

The device can be put into standby mode reducing power con-

sumption by more than 99% when deselected Chip Enable 1

(CE₁) HIGH or Chip Enable 2 (CE₂) LOW. The input/output

pins (I/O₀through I/O₇) are placed in a high-impedance state

when: deselected Chip Enable 1 (CE₁) HIGH or Chip Enable

2 (CE₂) LOW, outputs are disabled (OE HIGH), or during a

write operation (Chip Enable 1 (CE₁) LOW and Chip Enable 2

(CE₂) HIGH and Write Enable (WE) LOW).

Features

• Very high speed: 55 and 70 ns

• Wide voltage range: 2.2V to 3.6V

• Pin compatible with CY62128V

• Ultra-low active power

— Typical active current: 0.85 mA @ f = 1 MHz

— Typical active current: 5 mA @ f = f_MAX

• Ultra-low standby power

Writing to the device is accomplished by taking Chip Enable 1

(CE₁) LOW with Chip Enable 2 (CE₂) HIGH and Write En-

able(WE) LOW. Data on the eight I/O pins is then written into

the location specified on the Address pin (A₀thro. A₁₆).

• Easy memory expansion with CE₁, CE₂, and OE

features

• Automatic power-down when deselected

• Packages offered in a 32-lead SOIC, a 32-lead TSOP, a

32-lead Short TSOP, and a 32-lead Reverse TSOP

Reading from the device is accomplished by taking Chip En-

able 1 (CE₁) LOW with Chip Enable 2 (CE₂) HIGH and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins will appear on the I/O pins.

Functional Description^[1]

The CY62128DV30 is a high-performance CMOS static RAM

organized as 128K words by 8 bits. This device features ad-

vanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life (MoBL^®) in portable

applications such as cellular telephones. The device also has

an automatic power-down feature that significantly reduces

The eight input/output pins (I/O_othrough I/O₇) are placed in a

high-impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH) or

during a write operation (CE₁LOW, CE₂HIGH), and WE

LOW).

Logic Block Diagram

I/O

Data in Drivers

128K x 8

ARRAY

A10

A11

Power-

down

COLUMN

DECODER

I/O

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05231 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 29, 2003

12 3 4 5 6 7...11

中文翻译

下载PDF

与CY62128DV30相关器件

型号	品牌	获取价格	描述	数据表
CY62128DV30_06	CYPRESS	获取价格	1-Mb (128K x 8) Static RAM
CY62128DV30L-55SI	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 55ns, PDSO32, 0.450 INCH, SOIC-32
CY62128DV30L-55SI	CYPRESS	获取价格	1 Mb (128K x 8) Static RAM
CY62128DV30L-55ZAI	CYPRESS	获取价格	1 Mb (128K x 8) Static RAM
CY62128DV30L-55ZI	CYPRESS	获取价格	1 Mb (128K x 8) Static RAM
CY62128DV30L-55ZI	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 55ns, PDSO32, 8 X 20 MM, TSOP1-32
CY62128DV30L-55ZIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32
CY62128DV30L-55ZRI	CYPRESS	获取价格	1 Mb (128K x 8) Static RAM
CY62128DV30L-55ZRI	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 55ns, PDSO32, REVERSE, TSOP1-32
CY62128DV30L-55ZRIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, REVERSE, TSOP1-32

与CY62128DV30相关文章

BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

16
解读EGP10B二极管资料手册：产品特性、参数分析
2024-07-04

15
RT9164AGG手册资料详解：引脚信息、设计指南
2024-07-04

13
2SA1037KPT资料详解：产品特性、电气参数、设计指南
2024-07-04

16

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62128DV30

CY62128DV30 数据手册

与CY62128DV30相关器件

与CY62128DV30相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62128DV30

CY62128DV30 数据手册

与CY62128DV30相关器件

与CY62128DV30相关文章

您还可以找

您在本页遇到什么问题？