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CY62127DV30L-70ZIT PDF预览

CY62127DV30L-70ZIT

更新时间: 2024-02-06 02:07:20
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 547K
描述
Standard SRAM, 64KX16, 70ns, CMOS, PDSO44, TSOP2-44

CY62127DV30L-70ZIT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2,针数:44
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.83
最长访问时间:70 nsJESD-30 代码:R-PDSO-G44
JESD-609代码:e0长度:18.415 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:44
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.194 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

CY62127DV30L-70ZIT 数据手册

 浏览型号CY62127DV30L-70ZIT的Datasheet PDF文件第1页浏览型号CY62127DV30L-70ZIT的Datasheet PDF文件第2页浏览型号CY62127DV30L-70ZIT的Datasheet PDF文件第4页浏览型号CY62127DV30L-70ZIT的Datasheet PDF文件第5页浏览型号CY62127DV30L-70ZIT的Datasheet PDF文件第6页浏览型号CY62127DV30L-70ZIT的Datasheet PDF文件第7页 
CY62127DV30  
DC Input Voltage[5] ................................ 0.3V to VCC + 0.3V  
Maximum Ratings  
Output Current into Outputs (LOW)............................. 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature ..................................65°C to +150°C  
Latch-up Current.....................................................> 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage to Ground Potential  
......................................................................... 0.3V to 3.9V  
[6]  
Range  
Industrial  
Automotive  
Ambient Temperature (TA)  
–40°C to +85°C  
VCC  
2.2V to 3.6V  
2.2V to 3.6V  
DC Voltage Applied to Outputs  
in High-Z State[5] ....................................0.3V to VCC + 0.3V  
–40°C to +125°C  
DC Electrical Characteristics (Over the Operating Range)  
–45  
–55  
–70  
Parameter Description  
Test Conditions  
Min. Typ.[4] Max. Min. Typ.[4] Max. Min Typ.[4] Max. Unit  
VOH  
VOL  
VIH  
Output HIGH 2.2 < VCC < 2.7 IOH = 0.1 mA 2.0  
2.0  
2.4  
2.0  
2.4  
V
V
V
Voltage  
2.7 < VCC < 3.6 IOH = 1.0 mA 2.4  
Output LOW  
Voltage  
2.2 < VCC < 2.7 IOL = 0.1 mA  
2.7 < VCC < 3.6 IOL = 2.1 mA  
2.2 < VCC < 2.7  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
Input HIGH  
Voltage  
1.8  
2.2  
VCC 1.8  
+ 0.3  
VCC 1.8  
+ 0.3  
VCC  
+ 0.3  
2.7 < VCC < 3.6  
VCC 2.2  
+ 0.3  
VCC 2.2  
+ 0.3  
VCC  
+ 0.3  
VIL  
Input LOW  
Voltage  
2.2 < VCC < 2.7  
2.7 < VCC < 3.6  
0.3  
0.3  
0.6 0.3  
0.8 0.3  
0.6 0.3  
0.8 0.3  
0.6  
0.8  
V
IIX  
Input Leakage GND < VI < VCC  
Current  
Ind’l 1  
Auto  
+1  
1  
4  
1  
4  
+1  
+4  
+1  
+4  
1  
+1 µA  
µA  
IOZ  
Output  
GND < VO < VCC, Output Ind’l 1  
Disabled  
+1  
1  
+1 µA  
µA  
Leakage  
Current  
Auto  
ICC  
VCC Operating f = fMAX = 1/tRC VCC = 3.6V,  
6.5  
13  
5
10  
5
10 mA  
Supply Current  
IOUT = 0 mA,  
CMOS level  
f = 1 MHz  
0.85 1.5  
0.85 1.5  
0.85 1.5  
ISB1  
Automatic CE CE > VCC 0.2V,  
L
Ind’l  
1.5  
5
1.5  
1.5  
1.5  
5
15  
4
1.5  
5
µA  
µA  
Power-down  
Current—  
VIN > VCC 0.2V, VIN  
Auto  
< 0.2V,  
CMOS Inputs f = fMAX (Address and LL  
1.5  
4
1.5  
4
Data Only),  
f = 0 (OE, WE, BHE  
and BLE)  
ISB2  
Automatic CE CE > VCC 0.2V,  
L
Ind’l  
1.5  
1.5  
5
4
1.5  
1.5  
1.5  
5
15  
4
1.5  
1.5  
5
4
Power-down  
Current—  
V
IN > VCC 0.2V or  
Auto  
VIN < 0.2V,  
CMOS Inputs f = 0, VCC = 3.6V  
LL  
Capacitance[7]  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
pF  
CIN  
Input Capacitance  
Output Capacitance  
TA = 25°C, f = 1 MHz  
VCC = VCC(typ)  
8
8
COUT  
pF  
Notes:  
5. V  
= 2.0V for pulse durations less than 20 ns., V  
= Vcc+0.75V for pulse durations less than 20 ns.  
IH(max.)  
IL(min.)  
6. Full device operation requires linear ramp of V from 0V to V  
7. Tested initially and after any design or proces changes that may affect these parameters.  
& V must be stable at V  
for 500 µs.  
CC  
CC(min)  
CC  
CC(min)  
Document #: 38-05229 Rev. *H  
Page 3 of 11  
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