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CY54FCT827BTDMB PDF预览

CY54FCT827BTDMB

更新时间: 2024-10-01 19:42:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动输出元件逻辑集成电路
页数 文件大小 规格书
6页 141K
描述
Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, CDIP24, 0.300 INCH, CERDIP-24

CY54FCT827BTDMB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP24,.3
针数:24Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.5
其他特性:WITH DUAL OUTPUT ENABLE控制类型:ENABLE LOW
系列:FCTJESD-30 代码:R-GDIP-T24
JESD-609代码:e0长度:31.877 mm
负载电容(CL):300 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.032 A位数:10
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:6.5 ns传播延迟(tpd):14 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

CY54FCT827BTDMB 数据手册

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1CY54/74FCT827T  
fax id: 7005  
CY54/74FCT827T  
10-Bit Buffer  
Features  
Sink current  
64 mA (Com’l),  
32 mA (Mil)  
32 mA (Com’l),  
12 mA (Mil)  
Function, pinout and drive compatible with FCT, F, and  
AM29827 logic  
• FCT-C speed at 4.4ns max. (Com’l)  
FCT-A speed at 5.0ns max. (Com’l)  
• Reduced V  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature  
Source current  
Functional Description  
(typically = 3.3V) versions of equivalent  
OH  
The FCT827T 10-bit bus driver provides high-performance  
bus interface buffering for wide data/address paths or buses  
carrying parity. The 10-bit buffers have NAND-ed output  
enables for maximum control flexibility. The FCT827T is  
designed for high-capacitance load drive capability, while providing  
low-capacitance bus loading at both inputs and outputs. All outputs  
are designed for low-capacitance bus loading in the  
high-impedance state and are designed with a power-off disable  
feature to allow for live insertion of boards.  
ESD > 2000V  
• Matched rise and fall times  
• Fully compatible with TTL input and output logic levels  
Logic Block Diagram  
Pin Configurations  
LCC/PLCC  
Top View  
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
1110 9  
12  
8 7 6 5  
D
8
4
3
2
1
28  
27  
26  
D
D
0
1
D
GND  
NC  
13  
14  
15  
16  
17  
9
OE  
NC  
V
CC  
1
OE  
2
Y
9
Y
0
Y
8
18  
Y
1
19202122 23 24 25  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
OE OE  
1
2
DIP  
Top View  
1
OE  
1
24  
V
CC  
2
3
4
5
6
D
D
D
D
D
D
D
23  
22  
21  
Y
0
0
1
Y
1
Y
2
2
3
4
5
6
7
8
9
Y
3
20  
19  
18  
17  
16  
Y
4
Y
5
7
Y
6
8
D
D
D
9
Y
7
Y
8
10  
11  
12  
15  
14  
13  
Y
9
GND  
OE  
2
Function Table[1]  
Inputs  
Outputs  
Y
OE  
OE  
D
Function  
1
2
L
L
L
L
L
H
L
H
Transparent  
H
X
X
H
X
X
Z
Z
Three-State  
Note:  
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
September 1994 – Revised March 17, 1997  

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