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CY54FCT646ATLMB PDF预览

CY54FCT646ATLMB

更新时间： 2024-02-29 07:40:15
品牌 Logo 应用领域
德州仪器 - TI 输入元件输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 78K
描述
8-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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中文翻译

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CY54FCT646ATLMB 技术参数

生命周期：Active零件包装代码：QLCC
包装说明：LCC-28针数：28
Reach Compliance Code：not_compliantECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.18Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：FCTJESD-30 代码：S-CQCC-N28
长度：11.43 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.064 A位数：8
功能数量：1端口数量：2
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装等效代码：LCC28,.45SQ
封装形状：SQUARE封装形式：CHIP CARRIER
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：0.2 mA
Prop。Delay @ Nom-Sup：9 ns传播延迟（tpd）：7 ns
认证状态：Not Qualified施密特触发器：No
筛选级别：38535Q/M;38534H;883B座面最大高度：2.03 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：11.43 mm
Base Number Matches：1

CY54FCT646ATLMB 数据手册

 浏览型号CY54FCT646ATLMB的Datasheet PDF文件第2页浏览型号CY54FCT646ATLMB的Datasheet PDF文件第3页浏览型号CY54FCT646ATLMB的Datasheet PDF文件第4页浏览型号CY54FCT646ATLMB的Datasheet PDF文件第5页浏览型号CY54FCT646ATLMB的Datasheet PDF文件第6页浏览型号CY54FCT646ATLMB的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY54/74FCT646T  
SCCS031 - July 1994 - Revised March 2000  
8-Bit Registered Transceiver  
Features  
Functional Description  
• Function, pinout, and drive compatible with FCT and  
F logic  
• FCT-C speed at 5.4 ns max. (Com’l)  
FCT-A speed at 6.3 ns max. (Com’l)  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature permits live insertion  
• Matched rise and fall times  
• Fully compatible with TTL input and output logic levels  
• ESD > 2000V  
The FCT646T consists of a bus transceiver circuit with  
three-state, D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the input bus or  
from the internal registers. Data on the A or B bus will be  
clocked into the registers as the appropriate clock pin goes to  
a HIGH logic level. Enable Control G and direction pins are  
provided to control the transceiver function. In the transceiver  
mode, data present at the high-impedance port may be stored  
in either the A or B register, or in both. The select controls can  
multiplex stored and real-time (transparent mode) data. The  
direction control determines which bus will receive data when  
the enable control G is Active LOW. In the isolation mode  
(enable Control G HIGH), A data may be stored in the B reg-  
ister and/or B data may be stored in the A register.  
• Sink current  
Source current  
64 mA (Com’l), 48 mA (Mil)  
32 mA (Com’l), 12 mA (Mil)  
The outputs of the FCT646T are designed with a power-off  
disable feature to allow for live insertion of boards.  
• Independent register for A and B buses  
• Extended commercial range of −40˚C to +85˚C  
Function Block Diagrams  
Pin Configurations  
LCC  
QSOP, SOIC  
Top View  
G
Top View  
1
V
CPAB  
SAB  
DIR  
24  
CC  
DIR  
CPBA  
2
CPBA  
SBA  
G
23  
1110 9  
12  
13  
14  
8 7 6 5  
SBA  
CPAB  
SAB  
3
22  
A
7
4
3
2
1
DIR  
SAB  
4
A
1
21  
A
8
GND  
NC  
A
2
5
CPAB  
NC  
V
CC  
B
1
20  
15  
16  
17  
A
3
6
B
2
19  
18  
17  
16  
B
B
B
8
7
6
28  
27  
A
4
B
3
7
CPBA  
SBA  
A
5
B
4
18  
26  
8
D
19 20 21 22 23 24 25  
A
6
B
5
9
C
A
7
B
6
10  
11  
12  
15  
14  
A
8
B
7
GND  
B
8
13  
B
1 Logic Block Diagram  
A
1
D
C
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CPAB  
SAB  
DIR  
CPBA  
SBA  
G
B
B
B
B
B
B
B
B
8
1
2
3
4
5
6
7
TO 7 OTHER CHANNELS  
Pin Description  
Name  
Description  
A
Data Register A Inputs, Data Register B Outputs  
Data Register B Inputs, Data Register A Outputs  
Clock Pulse Inputs  
B
CPAB, CPBA  
SAB, SBA  
DIR, G  
Output Data Source Select Inputs  
Output Enable Inputs  
Copyright © 2000, Texas Instruments Incorporated  
12345678

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