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CY54FCT646TLMB PDF预览

CY54FCT646TLMB

更新时间： 2024-01-28 18:18:34
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路
页数 文件大小 规格书
8页 78K
描述
8-Bit Registered Transceiver

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CY54FCT646TLMB 数据手册

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Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY54/74FCT646T  
SCCS031 - July 1994 - Revised March 2000  
8-Bit Registered Transceiver  
Features  
Functional Description  
• Function, pinout, and drive compatible with FCT and  
F logic  
• FCT-C speed at 5.4 ns max. (Com’l)  
FCT-A speed at 6.3 ns max. (Com’l)  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature permits live insertion  
• Matched rise and fall times  
• Fully compatible with TTL input and output logic levels  
• ESD > 2000V  
The FCT646T consists of a bus transceiver circuit with  
three-state, D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the input bus or  
from the internal registers. Data on the A or B bus will be  
clocked into the registers as the appropriate clock pin goes to  
a HIGH logic level. Enable Control G and direction pins are  
provided to control the transceiver function. In the transceiver  
mode, data present at the high-impedance port may be stored  
in either the A or B register, or in both. The select controls can  
multiplex stored and real-time (transparent mode) data. The  
direction control determines which bus will receive data when  
the enable control G is Active LOW. In the isolation mode  
(enable Control G HIGH), A data may be stored in the B reg-  
ister and/or B data may be stored in the A register.  
• Sink current  
Source current  
64 mA (Com’l), 48 mA (Mil)  
32 mA (Com’l), 12 mA (Mil)  
The outputs of the FCT646T are designed with a power-off  
disable feature to allow for live insertion of boards.  
• Independent register for A and B buses  
• Extended commercial range of −40˚C to +85˚C  
Function Block Diagrams  
Pin Configurations  
LCC  
QSOP, SOIC  
Top View  
G
Top View  
1
V
CPAB  
SAB  
DIR  
24  
CC  
DIR  
CPBA  
2
CPBA  
SBA  
G
23  
1110 9  
12  
13  
14  
8 7 6 5  
SBA  
CPAB  
SAB  
3
22  
A
7
4
3
2
1
DIR  
SAB  
4
A
1
21  
A
8
GND  
NC  
A
2
5
CPAB  
NC  
V
CC  
B
1
20  
15  
16  
17  
A
3
6
B
2
19  
18  
17  
16  
B
B
B
8
7
6
28  
27  
A
4
B
3
7
CPBA  
SBA  
A
5
B
4
18  
26  
8
D
19 20 21 22 23 24 25  
A
6
B
5
9
C
A
7
B
6
10  
11  
12  
15  
14  
A
8
B
7
GND  
B
8
13  
B
1 Logic Block Diagram  
A
1
D
C
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CPAB  
SAB  
DIR  
CPBA  
SBA  
G
B
B
B
B
B
B
B
B
8
1
2
3
4
5
6
7
TO 7 OTHER CHANNELS  
Pin Description  
Name  
Description  
A
Data Register A Inputs, Data Register B Outputs  
Data Register B Inputs, Data Register A Outputs  
Clock Pulse Inputs  
B
CPAB, CPBA  
SAB, SBA  
DIR, G  
Output Data Source Select Inputs  
Output Enable Inputs  
Copyright © 2000, Texas Instruments Incorporated  
12345678

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