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CY39050V208-233NTXC PDF预览

CY39050V208-233NTXC

更新时间： 2024-01-23 07:51:30
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 输入元件可编程逻辑
页数 文件大小 规格书
86页 2802K
描述
Loadable PLD, 7.2ns, CMOS, PQFP208, 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208

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CY39050V208-233NTXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：FQFP,
针数：208Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.82
其他特性：ALSO OPERATES WITH 3.3V SUPPLY VOLTAGEJESD-30 代码：S-PQFP-G208
JESD-609代码：e3/e4长度：28 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：136端子数量：208
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 136 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装形状：SQUARE封装形式：FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：260可编程逻辑类型：LOADABLE PLD
传播延迟：7.2 ns认证状态：Not Qualified
座面最大高度：3.77 mm最大供电电压：2.7 V
最小供电电压：2.3 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN/NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：28 mmBase Number Matches：1

CY39050V208-233NTXC 数据手册

 浏览型号CY39050V208-233NTXC的Datasheet PDF文件第2页浏览型号CY39050V208-233NTXC的Datasheet PDF文件第3页浏览型号CY39050V208-233NTXC的Datasheet PDF文件第4页浏览型号CY39050V208-233NTXC的Datasheet PDF文件第5页浏览型号CY39050V208-233NTXC的Datasheet PDF文件第6页浏览型号CY39050V208-233NTXC的Datasheet PDF文件第7页 
Delta39K™ ISR™  
CPLD Family  
CPLDs at FPGA Densities™  
• Multiple I/O standards supported  
Features  
—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2  
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+  
• High density  
— 30K to 200K usable gates  
— 512 to 3072 macrocells  
— 136 to 428 maximum I/O pins  
• Compatible with NOBL™, ZBT™, and QDR™ SRAMs  
• Programmable slew rate control on each I/O pin  
• User-programmable Bus Hold capability oneach I/O pin  
— Twelve dedicated inputs including four clock pins,  
four global I/O control signal pins and four JTAG  
interface pins for boundary scan and reconfig-  
urability  
• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,  
rev. 2.2)  
• CompactPCI hot swap ready  
• Multiple package/pinout offering across all densities  
— 208 to 676 pins in PQFP, BGA, and FBGA packages  
—Simplifies design migration across density  
— Self-Boot™ solution in BGA and FBGA packages  
— Lead (Pb)-free packages available.  
• Embedded memory  
— 80K to 480K bits embedded SRAM  
• 16K to 96K bits of (dual-port) channel memory  
• High speed – 233-MHz in-system operation  
• AnyVolt™ interface  
• In-System Reprogrammable™ (ISR™)  
— 3.3V, 2.5V,1.8V, and 1.5V I/O capability  
• Low-power operation  
— JTAG-compliant on-board programming  
— Design changes do not cause pinout changes  
• IEEE1149.1 JTAG boundary scan  
— 0.18-mm six-layer metal SRAM-based logic process  
— Full-CMOS implementation of product term array  
— Standby current as low as 5mA  
Development Software  
• Simple timing model  
• Warp®  
— No penalty for using full 16 product terms/macrocell  
— No delay for single product term steering or sharing  
• Flexible clocking  
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context  
sensitive editing  
— Spread Aware™ PLL drives all four clock networks  
• Allows 0.6% spread spectrum input clocks  
• Several multiply, divide and phase shift options  
— Four synchronous clock networks per device  
—Locally generated product term clock  
— Clock polarity control at each register  
— Active-HDL FSM graphical finite state machine editor  
— Active-HDL SIM post-synthesis timing simulator  
— Architecture Explorer for detailed design analysis  
— Static Timing Analyzer for critical path analysis  
— Available on Windows® 95/98/2000/XP™ and  
Windows NT™ for $99  
— Supports all Cypress programmable logic products  
• Carry-chain logic for fast and efficient arithmetic opera-  
tions  
Delta39K™ ISR CPLD Family Members  
[2]  
Standby ICC  
Cluster Channel  
Speed-tPD  
TA = 25°C  
3.3/2.5V  
5 mA  
Typical  
Gates[1]  
memory memory Maximum fMAX2 Pin-to-Pin  
Device  
39K30  
Macrocells  
512  
(Kbits)  
64  
(Kbits)  
16  
I/O Pins  
174  
(MHz)  
233  
(ns)  
7.2  
7.2  
7.5  
8.5  
16K – 48K  
23K – 72K  
46K – 144K  
92K – 288K  
39K50  
768  
96  
24  
218  
233  
5 mA  
39K100  
39K200  
1536  
192  
384  
48  
302  
222  
10 mA  
20 mA  
3072  
96  
428  
181  
Notes:  
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.  
2. Standby I values are with PLL not utilized, no output load and stable inputs.  
CC  
Cypress Semiconductor Corporation  
Document #: 38-03039 Rev. *I  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised March 11, 2005  
[+] Feedback  
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CY39050V208-233NTXC 替代型号

型号 品牌 替代类型 描述 数据表
CY39050V208-125NTXC CYPRESS

完全替代

 Loadable PLD, 10ns, CMOS, PQFP208, 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208

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