Delta39K™ ISR™
CPLD Family
PRELIMINARY
CPLDs at FPGA Densities™
• Multiple I/O standards supported
Features
—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
• High density
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
— 30K to 200K usable gates
— 512 to 3072 macrocells
— 136 to 428 maximum I/O pins
• Compatible with NOBL™, ZBT™, and QDR™ SRAMs
• Programmable slew rate control on each I/O pin
• User-Programmable Bus Hold capability on each I/O pin
• Fully PCI compliant (to 66 MHz 64-bit PCI spec, rev. 2.2)
• CompactPCI hot swap ready
• Multiple package/pinout offering across all densities
—208 to 676 pins in PQFP, BGA, and FBGA packages
—Same pinout for 3.3V/2.5V and 1.8V devices
—Simplifies design migration across density
—Self-Boot™ solution in BGA and FBGA packages
• In-System Reprogrammable™ (ISR™)
— Twelve dedicated inputs including four clock pins, four
global I/O control signal pins and four JTAG interface
pins for boundary scan and reconfigurability
• Embedded memory
— 80K to 480K bits embedded SRAM
• 64K to 384K bits of (single-port) cluster memory
• 16K to 96K bits of (dual-port) channel memory
• High speed – 233-MHz in-system operation
• AnyVolt™ interface
—JTAG-compliant on-board programming
— 3.3V, 2.5V, and 1.8V VCC versions available
—Design changes don’t cause pinout changes
• IEEE1149.1 JTAG boundary scan
— 3.3V, 2.5V, and 1.8V I/O capability on all versions
• Low-power operation
— 0.18-µm six-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
Development Software
— Standby current as low as 200 µA at 1.8V VCC
• Simple timing model
• Warp®
—IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— No penalty for using full 16 product terms / macrocell
— No delay for single product term steering or sharing
• Flexible clocking
—Active-HDL FSM graphical finite state machine editor
—Active-HDL SIM post-synthesis timing simulator
—Architecture Explorer for detailed design analysis
—Static Timing Analyzer for critical path analysis
— four synchronous clocks per device
— One spread-aware PLL drives all four clock networks
— Locally generated product term clock
— Clock polarity control at each register
• Carry-chain logic for fast and efficient arithmetic operations
—Available on Windows 95™, Windows 98™ and
Windows NT™ for $99
—Supports all Cypress programmable logic products
Delta39K™ ISR CPLD Family Members
[2]
Standby ICC
Cluster Channel
Speed-tPD
TA = 25°C
Typical
Gates[1]
memory memory Maximum fMAX2 Pin-to-Pin
Device
39K30
Macrocells
512
(Kbits)
64
(Kbits)
16
I/O Pins
176
(MHz)
233
(ns)
7.2
7.2
7.5
8.5
8.5
3.3/2.5V
1.8V
16K – 48K
23K – 72K
46K – 144K
77K – 241K
92K – 288K
10 mA
10 mA
10 mA
10 mA
10 mA
200 µA
300 µA
600 µA
1250 µA
1250 µA
39K50
768
96
24
218
233
39K100
39K165
39K200
1536
192
320
384
48
302
222
2560
80
386
181
3072
96
428
181
Notes:
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2. Standby ICC values are with PLL not utilized, no output load and stable inputs.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03039 Rev. *C
December 21, 2001