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CY29FCT520ATSOCT

更新时间： 2024-09-29 22:21:35
品牌 Logo 应用领域
德州仪器 - TI 外围集成电路光电二极管输出元件
页数 文件大小 规格书
13页 262K
描述
Multi-Level Pipeline Register

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CY29FCT520ATSOCT 数据手册

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CY29FCT520T  
MULTILEVEL PIPELINE REGISTER  
WITH 3-STATE OUTPUTS  
SCCS011C – MAY 1994 – REVISED NOVEMBER 2001  
D, P, OR SO PACKAGE  
(TOP VIEW)  
Function, Pinout, and Drive Compatible  
With FCT, F Logic, and AM29520  
Reduced V  
Equivalent FCT Functions  
(Typically = 3.3 V) Version of  
V
OH  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
I
I
CC  
0
0
1
0
1
2
3
4
5
6
7
S
S
Y
Y
Y
Y
Y
Y
Y
Y
2
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
3
D
D
D
D
D
D
D
D
1
4
0
5
1
6
I
Supports Partial-Power-Down Mode  
2
off  
7
Operation  
3
8
4
Matched Rise and Fall Times  
9
5
Fully Compatible With TTL Input and  
Output Logic Levels  
10  
11  
12  
6
CLK  
GND  
7
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
13 OE  
– 1000-V Charged-Device Model (C101)  
Single- and Dual-Pipeline Operation Modes  
Multiplexed Data Inputs and Outputs  
CY29FCT520T  
– 64-mA Output Sink Current  
32-mA Output Source Current  
CY29FCT520ATDMB, CY29FCT520BTDMB  
– 32-mA Output Sink Current  
12-mA Output Source Current  
3-State Outputs  
description  
The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1,  
and B2, which are configured by the instruction inputs I , I as a single four-level pipeline or as two two-level  
0
1
pipelines. The contents of any register can be read at the multiplexed output at any time by using the  
multiplex-selection controls (S and S ).  
0
1
The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input.  
Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2  
selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.  
In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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CY29FCT520ATSOCT 替代型号

型号 品牌 替代类型 描述 数据表
CY29FCT520ATSOCTG4 TI

完全替代

 8-Bit Multi-Level Pipeline Register 24-SOIC -40 to 85
CY29FCT520BTSOC TI

完全替代

 Multi-Level Pipeline Register
CY29FCT520ATSOC TI

完全替代

 Multi-Level Pipeline Register

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CY29FCT520BTSOCTE4 TI

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