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CY29FCT52ATDMB PDF预览

CY29FCT52ATDMB

更新时间: 2024-11-21 20:10:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 101K
描述
Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, CDIP24, 0.300 INCH, CERDIP-24

CY29FCT52ATDMB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP24,.3
针数:24Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.77
其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:FCT
JESD-30 代码:R-GDIP-T24JESD-609代码:e0
长度:31.877 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.048 A
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):11 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:7.62 mmBase Number Matches:1

CY29FCT52ATDMB 数据手册

 浏览型号CY29FCT52ATDMB的Datasheet PDF文件第2页浏览型号CY29FCT52ATDMB的Datasheet PDF文件第3页浏览型号CY29FCT52ATDMB的Datasheet PDF文件第4页浏览型号CY29FCT52ATDMB的Datasheet PDF文件第5页浏览型号CY29FCT52ATDMB的Datasheet PDF文件第6页浏览型号CY29FCT52ATDMB的Datasheet PDF文件第7页 
T
fax id: 7032  
CY29FCT52T  
8-Bit Registered Transceiver  
Features  
Sink Current  
64 mA (Com’l),  
48 mA (Mil)  
32 mA (Com’l),  
12 mA (Mil)  
Function, pinout, and drive compatible with FCT,  
Source Current  
F Logic and AM2952  
FCT-C speed at 6.3 ns max. (Com’l)  
FCT-B speed at 7.5 ns max. (Com’l)  
Reduced V (typically = 3.3V) versions of equivalent  
FCT functions  
Edge-rate control circuitry for significantly improved  
noise characteristics  
Functional Description  
OH  
The CY29FCT52T has two 8-bit back-to-back registers that  
store data flowing in both directions between two bidirectional  
buses. Separate clock, clock enable, and three-state output  
enable signals are provided for each register. Both A outputs  
and B outputs are guaranteed to sink 64 mA.  
ESD > 2000V  
Power-off disable feature  
Matched rise and fall times  
Fully compatible with TTL input and output logic levels  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
Logic Block Diagram  
Pin Configurations  
CPA  
CEA  
OEB  
CE CP  
A
D
Q
0
B
0
0
0
SOIC/QSOP  
Top View  
A
1
B
1
D
1
Q
1
A
2
B
2
D
2
Q
2
1
24  
A
B
B
B
B
B
B
V
CC  
7
3
3
4
5
6
7
D
Q
3
3
2
B
23  
22  
21  
6
A
4
A
7
D
4
Q
4
3
B
5
A
6
A
5
D
5
Q
5
4
B
4
A
5
A
6
D
6
Q
6
5
B
20  
19  
18  
17  
16  
3
A
4
A
7
D
7
Q
7
6
B
2
A
3
B
1
7
A
2
B
0
8
A
1
Q
0
D
0
OEB  
CPA  
CEA  
GND  
9
A
0
Q
1
D
1
10  
11  
12  
OEA  
CPB  
15  
14  
Q
2
D
2
Q
3
D
3
CEB  
13  
Q
4
D
4
Q
5
D
5
Q
6
D
6
CE CP  
Q
7
D
7
OEA  
CPB  
CEB  
]
Function Table[1]  
Output Control  
OE  
Internal Q Y-Outputs  
Function  
Inputs  
H
X
Z
Disable Outputs  
Enable Outputs  
D
CP  
CE  
Internal Q  
Function  
Hold Data  
Load Data  
L
L
L
H
L
H
X
X
H
NC  
L
H
L
L
L
H
Note:  
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
May 1994 – Revised December 1, 1997  

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