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CY14B104K_1106 PDF预览

CY14B104K_1106

更新时间: 2024-02-07 17:57:42
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器时钟
页数 文件大小 规格书
35页 1030K
描述
4-Mbit (512 K x 8/256 K x 16) nvSRAM with Real Time Clock 25 ns and 45 ns access times

CY14B104K_1106 数据手册

 浏览型号CY14B104K_1106的Datasheet PDF文件第2页浏览型号CY14B104K_1106的Datasheet PDF文件第3页浏览型号CY14B104K_1106的Datasheet PDF文件第4页浏览型号CY14B104K_1106的Datasheet PDF文件第5页浏览型号CY14B104K_1106的Datasheet PDF文件第6页浏览型号CY14B104K_1106的Datasheet PDF文件第7页 
CY14B104K, CY14B104M  
4-Mbit (512 K × 8/256 K × 16) nvSRAM  
with Real Time Clock  
4-Mbit (512  
K × 8/256 K × 16) nvSRAM with Real Time Clock  
Watchdog timer  
Features  
Clock alarm with programmable interrupts  
Capacitor or battery backup for RTC  
25 ns and 45 ns access times  
Internally organized as 512 K × 8 (CY14B104K) or 256 K × 16  
(CY14B104M)  
Industrial temperature  
Hands off automatic STORE on power-down with only a small  
capacitor  
44-pin and 54-pin thin small outline package (TSOP) Type II  
Pb-free and restriction of hazardous substances (RoHS)  
compliant  
STORE to QuantumTrap non-volatile elements is initiated by  
software, device pin, or AutoStore on power-down  
Functional Description  
RECALL to SRAM is initiated by software or power-up  
High reliability  
The Cypress CY14B104K and CY14B104M combines a 4-Mbit  
non-volatile static RAM (nvSRAM) with a full-featured RTC in a  
monolithic integrated circuit. The embedded non-volatile  
elements incorporate QuantumTrap technology producing the  
world’s most reliable non-volatile memory. The SRAM is read  
and written infinite number of times, while independent  
non-volatile data resides in the non-volatile elements.  
Infinite read, write, and RECALL cycles  
1 million STORE cycles to QuantumTrap  
20 year data retention  
Single 3 V +20%, –10% operation  
The RTC function provides an accurate clock with leap year  
tracking and a programmable, high accuracy oscillator. The  
alarm function is programmable for periodic minutes, hours,  
days, or months alarms. There is also a programmable watchdog  
timer for process control.  
Data integrity of Cypress nvSRAM combined with full-featured  
real time clock (RTC)  
Logic Block Diagram [1, 2, 3]  
VCC  
VCA  
Quatrum  
P
Trap  
2048 X 2048  
VRTCbat  
A0  
A1  
A2  
POWER  
CONTROL  
R
STORE  
VRTCcap  
O
W
RECALL  
A3  
A4  
A5  
A6  
A7  
A8  
A17  
STORE/RECALL  
HSB  
D
E
C
O
D
E
R
CONTROL  
STATIC RAM  
ARRAY  
2048 X 2048  
SOFTWARE  
A14 - A2  
DETECT  
A18  
DQ0  
DQ1  
DQ2  
Xout  
Xin  
DQ3  
DQ4  
RTC  
MUX  
I
INT  
N
P
U
T
B
U
F
F
E
R
S
DQ5  
DQ6  
DQ7  
COLUMN I/O  
A18- A0  
DQ8  
DQ9  
DQ10  
OE  
COLUMN DEC  
WE  
DQ11  
DQ12  
DQ13  
DQ14  
CE  
BLE  
A9 A10  
A
11 A12 A13 A14 A15 A16  
DQ15  
BHE  
Notes  
1. Address A –A for × 8 configuration and Address A –A for × 16 configuration.  
0
18  
0
17  
2. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.  
0
7
0
15  
3. BHE and BLE are applicable for × 16 configuration only.  
Cypress Semiconductor Corporation  
Document #: 001-07103 Rev. *U  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 12, 2011  
[+] Feedback  

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