Datasheet > CXD2597Q

CXD2597Q

更新时间： 2022-12-01 17:16:52

品牌	Logo	应用领域
索尼 - SONY		数字信号处理器
页数	文件大小	规格书
115页	870K
描述
CD Digital Signal Processor with Built-in Digital Servo and DAC

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数据手册

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CXD2597Q 数据手册

CXD2597Q

No.

Symbol

I/O

Description

LOUT1

AVSS1

AVSS2

LOUT2

AIN2

—

L ch LINE output.

Analog GND.

—

Analog GND.

R ch LINE output.

R ch operational amplifier output.

R ch analog output.

AOUT2

AVDD2

RMUT

LMUT

—

Analog power supply.

1, 0

R ch zero detection flag.

L ch zero detection flag.

Notes) • PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window opens.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the

EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XROF is generated when the 16K RAM exceeds the ±4F jitter margin.

Monitor Pin Output Combinations

Command bit

Output data

MTSL1 MTSL0

XUGF

MNT1

RFCK

XPCK

MNT0

XPCK

GFS

MNT3

XROF

C2PO

GTOP

– 6 –

1...3 4 567 8 9...115

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