Datasheet > CVPD-970

CVPD-970

更新时间： 2024-09-24 03:27:27

品牌	Logo	应用领域
CRYSTEKMICROWAVE		石英晶振压控振荡器
页数	文件大小	规格书
2页	126K
描述
Differential LVPECL VCXO 9X14 mm SMD, 3.3V, LVPECL

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中文翻译

获取价格

数据手册

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CVPD-970 数据手册

CVPD-970 Model

9X14 mm SMD, 3.3V, LVPECL

Frequency Range:

622.08MHz to 670MHz

Frequency Stability:

Temperature Range:

±25ppm

0°C to 70°C

-40°C to 85°C

(Option X)

Storage:

-55°C to 120°C

Input Voltage:

Control Voltage:

Input Current:

3.3V ± 0.3V

1.65V ± 1.65V

80mA Max

Output:

Differential LVPECL

49/51% Typ, 45/55% Max

0.4ns Max @ 20% to 80% Vcc

± 50ppm Min.

Symmetry:

Rise/Fall Time:

Pullability APR:

Linearity:

± 10% Max

Load: Terminated to Vdd-2V into 50 ohms

Logic "1" Level:

Logic "0" Level:

Disable Time:

Start-up Time:

Vcc-0.96V Min, Vcc-0.81V Max

Vcc-1.85V Min, Vcc-1.65V Max

100ns Max

2ms Typ., 10ms Max

Modulation BW:

>10KHz @ -3dB

-40dBc

Sub-harmonics:

Period Jitter: (20,000 periods)

Phase Jitter: 12KHz~20MHz

50KHz~80MHz

<5ps RMS (1-sigma) Max

<1ps RMS (1-sigma) Max,

Phase Noise Typical: 100Hz

-80 dBc/Hz

-108 dBc/Hz

-132 dBc/Hz

-140 dBc/Hz

1KHz

10KHz

100KHz

Aging:

<3ppm 1st/yr, <2ppm every year thereafter

Applications:

10 Gigabit Ethernet

OC192: Forward Error Correction

Broadband Networks

SONET/SDH/DWD

ATM

Network/switch

Telecom

Designed using FR5 PCB & HFF crystal technology to

provide a very Low Noise, Low Jitter Voltage Controlled

Clock Oscillator solution at a competitive price.

TD-030607 Rev.C

Specifications subject to change without notice.

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